Patents by Inventor Aditya Chaudhary

Aditya Chaudhary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12228655
    Abstract: This disclosure is directed to shared antenna tuning. An electronic device may receive a global navigation satellite system (GNSS) tune request to tune a shared antenna to a GNSS signal frequency. The electronic device may then tune the antenna to the GNSS signal frequency and enable a GNSS receiver. The electronic device may also receive a cellular tune request to tune the antenna to a cellular frequency. The electronic device may tune the antenna to a cellular frequency and may deactivate the GNSS receiver or blank the GNSS receiver. In some embodiments, the electronic device may also communicate with a Low Earth Orbit (LEO) satellite. During LEO satellite communication, the electronic device may transmit a signal to blank a GNSS L1 receiver to avoid signal interference with the LEO satellite communication, and activate a GNSS L5 receiver to receive GNSS signals.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: February 18, 2025
    Assignee: Apple Inc.
    Inventors: Glenn D. MacGougan, Aditya N. Srivastava, Harsha Shirahatti, Madhusudan Chaudhary, Ozgur Ekici, Sachin J. Sane, William J. Bencze
  • Patent number: 9330225
    Abstract: Design errors generated employing a mask rule check (MRC) program are indexed and examined one by one by an automated computer program connected to a false error pattern database that contains previously known waivered patterns, a real error pattern database that contains previously known pairs of an error-containing pattern and a corresponding error-free pattern, and optionally a mask house rule database. A waiver is applied to each design error for which a matching pattern is found in the false error pattern database. Each design error for which a match is found in the real error pattern database is modified to substitute an error-free pattern for an error-containing pattern therein. The output of the automated program includes a list of design errors for which no solution is found by the automated program.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: May 3, 2016
    Assignee: International Business Machines Corporation
    Inventors: Aditya Chaudhary, Kalpesh G. Dave, Mini M. Ghosal, Ioana Graur, Bhavani P. Kumar
  • Publication number: 20150356228
    Abstract: Design errors generated employing a mask rule check (MRC) program are indexed and examined one by one by an automated computer program connected to a false error pattern database that contains previously known waivered patterns, a real error pattern database that contains previously known pairs of an error-containing pattern and a corresponding error-free pattern, and optionally a mask house rule database. A waiver is applied to each design error for which a matching pattern is found in the false error pattern database. Each design error for which a match is found in the real error pattern database is modified to substitute an error-free pattern for an error-containing pattern therein. The output of the automated program includes a list of design errors for which no solution is found by the automated program.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Applicant: International Business Machines Corporation
    Inventors: Aditya Chaudhary, Kalpesh G. Dave, Mini M. Ghosal, Ioana Graur, Bhavani P. Kumar
  • Patent number: 8495525
    Abstract: A library of waivable images with corresponding waiver constraints is generated. Each of the waivable images is an image of a region of a reference design layout including a raw error as determined by an optical rule checks (ORC) program and does not require a correction for printability on a photoresist layer. A list of raw errors is generated by running the ORC program on a target design layout. Error region images corresponding to the list of raw errors are generated by selecting a region of the target design layout around points corresponding to the raw errors. A list of matches between the library of waivable images and the error region images is generated. By removing a subset of raw errors that correspond to a subset of the list of matches from the list of raw errors, a list of real errors is generated.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Aditya Chaudhary, Pierre J. Bouchard, Kalpesh G. Dave