Patents by Inventor Aditya Chityala

Aditya Chityala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Real-time mathematical model for wafer spin defect detection and for misalignment analyses
    Patent number: 7127359
    Abstract: According to various embodiments, there is a method of inspecting semiconductor wafers comprising comparing a value for each wafer in a lot of wafers to a mathematical model, where the values include data about at least one feature on the wafers, and where the mathematical model comprises a threshold value corresponding to the at least one feature, and further where values greater than the threshold value comprise an indication of a spin defect. The method can also comprise determining whether any of the values of the wafers in the lot are not greater than the threshold value, grouping into a group (P) those wafers whose values are not greater than the threshold value, and flagging for further inspection those wafers having values greater than the threshold value.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: October 24, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Aditya Chityala, Errol Philip Akomer, Jason Charles Tervooren
  • Real-time mathematical model for wafer spin defect detection and for misalignment analyses
    Publication number: 20060212245
    Abstract: According to various embodiments, there is a method of inspecting semiconductor wafers comprising comparing a value for each wafer in a lot of wafers to a mathematical model, where the values include data about at least one feature on the wafers, and where the mathematical model comprises a threshold value corresponding to the at least one feature, and further where values greater than the threshold value comprise an indication of a spin defect. The method can also comprise determining whether any of the values of the wafers in the lot are not greater than the threshold value, grouping into a group (P) those wafers whose values are not greater than the threshold value, and flagging for further inspection those wafers having values greater than the threshold value.
    Type: Application
    Filed: March 1, 2005
    Publication date: September 21, 2006
    Inventors: Aditya Chityala, Errol Akomer, Jason Tervooren