Patents by Inventor Aditya Gujja

Aditya Gujja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Muller C-element as majority gate for self-correcting triple modular redundant logic with low-overhead modes
    Patent number: 9780788
    Abstract: Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 3, 2017
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Srivatsan Chellappa, Vinay Vashishtha, Aditya Gujja
  • MULLER C-ELEMENT AS MAJORITY GATE FOR SELF-CORRECTING TRIPLE MODULAR REDUNDANT LOGIC WITH LOW-OVERHEAD MODES
    Publication number: 20170117895
    Abstract: Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.
    Type: Application
    Filed: October 24, 2016
    Publication date: April 27, 2017
    Applicant: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Srivatsan Chellappa, Vinay Vashishtha, Aditya Gujja