Abstract: The present disclosure provides an assay device and associated method(s) to facilitate the determination of risk of a subject to develop severe forms of SARS-CoV2 infection. Said determination of risk or genetic predisposition to severe forms of SARS-CoV2 infection employing the assay device and associated method(s) relies on specifically designed CRISPR-Cas system(s). Said CRISPR-Cas system(s) employed in the present disclosure are further characterized by unique guide sequences that enable detection of presence or absence of specific Single Nucleotide Polymorphisms (SNPs) in a sample, wherein the SNPs have a genetic correlation with severe forms of SARS-CoV2 infection.

Abstract: Systems or methods of the present disclosure may provide systems and techniques for controlling access to components and resources of an IC device by multiple tenants. For example, a method may include: receiving access control instructions defining a first mapping between one or more tenants and respective security attributes and a second mapping between one or more agent identifiers and respective access permissions; receiving a communication intended for a target component of the IC device; determining an origin tenant from which the communication originated; determining a security attribute associated with the origin tenant based on the first mapping; and sending the communication and an agent identifier comprising the security attribute and an initiator bridge identifier to a corresponding target bridge, wherein the corresponding target bridge is configured to grant or deny access of the communication to the target component based on the agent identifier and the second mapping.

Abstract: Implementations disclose selecting, in response to receiving a request and from among multiple candidate generative models (e.g., multiple candidate large language models (LLMs)) with differing computational efficiencies, a particular generative model to utilize in generating a response to the request. Those implementations reduce latency and/or conserve computational resource(s) through selection, for various requests, of a more computationally efficient generative model for utilization in lieu of a less computationally efficient generative model. Further, those implementations seek to achieve such benefits, through utilization of more computationally efficient generative models, while also still selectively utilizing less computationally efficient generative models for certain requests to mitigate occurrences of a generated response being inaccurate and/or under-specified.

Abstract: This application relates to apparatus and methods for providing recommended items to advertise. In some examples, a computing device determines a first set of items for recommendation based on historical user data associated with a user, and a second set of items for recommendation based on real-time user session data for the user. The computing device may then determine a subset of the first set of items based on associated scores and a predetermined threshold number of first items that can be presented for optimal user interaction. The computing device may generate a set of item recommendations by combining the subset of the first set of items and at least one of the second set of items to present to the user as advertisements.

Abstract: Provided are systems and methods for real-time identification of fraudulent users of an online resource such as a website or mobile application, including new user accounts that have yet to transact on the online resource. In one example, a method may include receiving, by a host platform of an online resource, a request from a user device associated with a user account of the online resource, creating, by the host platform, a device fingerprint of the user device based on a plurality of device attributes included in the request, determining, by the host platform, whether the device fingerprint matches a previously banned device fingerprint stored in a database by the online resource, and in response to a determination that the device fingerprint has been banned previously, automatically restricting, by the host platform, an ability of the user account with the online resource.

Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

Abstract: A data processing system for extracting metadata values is described. The data processing system includes an input unit and a processor communicably coupled to the input unit. The input unit is configured to receive a contract document. The processor is configured to extract at least one segment from the contract document and identify a type of the at least one segment. The processor is further configured to extract at least one metadata value from the at least one segment based on a model, wherein the model is determined based on the identified type of the at least one segment.

Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

Abstract: A method (200) for configuring a workflow is described. The method (200) comprises initiating (202), by a workflow engine (122), a task in the workflow and identifying (210), by a rule engine (124), at least one upcoming task in the workflow based on data associated with at least one parameter of the task. The method (200) further comprises determining (212), by a task engine (126), at least one additional parameter of the identified at least one upcoming task and obtaining (214), by the task engine (126), data associated with the at least one additional parameter. The method (200) further comprises completing (216), by the task engine (126), the task based on the data associated with the at least one additional parameter.

Abstract: Implementing an application using a plurality of data processing engines (DPEs) can include, in a first pass, mapping, using computer hardware, a data flow graph onto an array of DPEs by minimizing direct memory access (DMA) circuit usage and memory conflicts in the array of DPEs and, in response to determining that a mapping solution generated by the first pass requires an additional DMA circuit not specified by the data flow graph, inserting, using the computer hardware, additional buffers into the data flow graph. In a second pass, the additional buffers can be mapped, using the computer hardware, onto the array of DPEs by minimizing the memory conflicts in the array of DPEs.

Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Abstract: According to one aspect of the present disclosure, a computing device is provided, including non-volatile memory storing a database including a plurality of database entries. The computing device may further include a processor configured to sort the plurality of database entries into a plurality of database entry length sets. For each database entry length set, each database entry included in the database entry length set may be within a predefined length range. For each database entry length set, the processor may be further configured to generate a probabilistic data structure based on the one or more database entries included in the database entry length set.

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bitstream and/or binary code which configures programmable and non-programmable logic in a heterogeneous processing environment of a SoC to execute the graph. The compiler can also consider user-defined constraints when compiling the source code. The constraints can dictate where the kernels and buffers should be placed in the heterogeneous processing environment, performance requirements, data communication routes through the SoC, type of data path, delays, and the like.

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Abstract: For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.