Patents by Inventor Aditya Kasukurti

Aditya Kasukurti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING
    Publication number: 20240088296
    Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Erica J. THOMPSON, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
  • Nanowire transistor structure and method of shaping
    Patent number: 11869973
    Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
  • Transistor device with (anti)ferroelectric spacer structures
    Patent number: 11640984
    Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: May 2, 2023
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Ian Young, Matthew Metz, Uygar Avci, Chia-Ching Lin, Owen Loh, Seung Hoon Sung, Aditya Kasukurti, Sou-Chi Chang, Tanay Gosavi, Ashish Verma Penumatcha
  • TRANSISTOR DEVICE WITH (ANTI)FERROELECTRIC SPACER STRUCTURES
    Publication number: 20200312978
    Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Jack KAVALIEROS, Ian YOUNG, Matthew METZ, Uygar AVCI, Chia-Ching LIN, Owen LOH, Seung Hoon SUNG, Aditya KASUKURTI, Sou-Chi CHANG, Tanay GOSAVI, Ashish Verma PENUMATCHA
  • NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING
    Publication number: 20190393350
    Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Applicant: INTEL CORPORATION
    Inventors: Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie