Abstract: The invention includes an integrated circuit. The integrated circuit includes a test controller, at least one logic unit controller, and a test bus connected between the test controller and the logic unit controller. A design for test feature is connected to the logic unit controller. Moreover, a logic unit can be connected to the design for test feature.

Abstract: The invention includes an integrated circuit (IC). The IC includes an internal test bus (ITB). The IC also includes a number of deskew clusters connected to the ITB. The deskew clusters each include a deskew controller. The IC also includes an integrated test controller (ITC) connected to the ITB. Further, the IC includes a debug unit connected to the ITC. The ITC generates a single global control signal and the deskew controller generates a first local command signal.

Abstract: A function for adaptively generating test vectors to verify the behavior of a digital system. The function utilizes one or more user-defined verification directives for directing the generation of the test vectors to areas of interest within the digital system. An emulator of the digital system provides dynamic feedback of internal state information to the test vector generation function during the verification. The test vector generation function adaptively generates future verification test vectors based on the user-defined verification directives in view of the internal state information feedback received from the emulator.

Abstract: The invention includes an integrated circuit (IC). The IC may include an internal test bus (ITB). The IC may also include a number of deskew clusters connected to the ITB. The deskew clusters each include a deskew controller. The IC may also include an integrated test controller (ITC) connected to the ITB. Further, the IC may include a debug unit connected to the ITC. The ITC generates a single global control signal and the deskew controller generates a first local command signal.