Patents by Inventor Aditya Pradeep Karmarkar
Aditya Pradeep Karmarkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180144073Abstract: Oxidation of high aspect ratio IC structures, such as pillars and fins, can deform them. Disclosed is technology for simulating the deformation efficiently so that process conditions or pattern design can be altered to improve manufacturability. A database describing a 3D model of the structures prior to the oxidation process is provided. Oxidation is simulated in 1D on different surfaces to estimate a depth of starting material that will be converted during oxidation. Starting material is then replaced to that depth on all surfaces, by oxide with known expansion ratio. An initial mechanical stress and strain field is determined based on the model in dependence upon the replacement depth and the expansion ratio, and the system relaxes the fields to their equilibrium states, which include the deformations. The deformations are reported to a user, who can repeat the process using different oxidizing conditions and/or patterns to optimize manufacturability.Type: ApplicationFiled: August 16, 2017Publication date: May 24, 2018Applicant: Synopsys, Inc.Inventors: Xiaopeng Xu, Aditya Pradeep Karmarkar, Karim El Sayed
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Patent number: 9275182Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: GrantFiled: March 31, 2015Date of Patent: March 1, 2016Assignee: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Publication number: 20150205904Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Applicant: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Patent number: 9003348Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: GrantFiled: February 24, 2014Date of Patent: April 7, 2015Assignee: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Publication number: 20140173545Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: ApplicationFiled: February 24, 2014Publication date: June 19, 2014Applicant: SYNOPSYS, INC.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Patent number: 8661387Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: GrantFiled: January 14, 2013Date of Patent: February 25, 2014Assignee: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Publication number: 20130132914Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: ApplicationFiled: January 14, 2013Publication date: May 23, 2013Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Patent number: 8362622Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: GrantFiled: April 24, 2009Date of Patent: January 29, 2013Assignee: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Publication number: 20100270597Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: ApplicationFiled: April 24, 2009Publication date: October 28, 2010Applicant: SYNOPSYS, INC.Inventors: JAMES DAVID SPROCH, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar