Abstract: A method for affecting operation of building equipment includes providing a plurality of reliability models that model failure probabilities of components of the building equipment as functions of equipment runtime, providing associations of the components with a plurality of subsystems of the building equipment, calculating, for the plurality of subsystems of the building equipment, probabilities of subsystem failure based on the reliability models for the components and the associations, and initiating an automated action to affect operation of the building equipment based on the probabilities of subsystem failure.

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

Abstract: All existing state-of-the-art high resolution millimeter wave imaging systems experience a trade off between image acquisition time and transceiver array complexity. The proposed dual reflector antenna breaks this trade-off by drastically reducing the array formation time while maintaining the relative simplicity that comes with using a single transceiver element. It consists of a dual mode horn feed, a rotating ellipsoidal sub-reflector and a conic main reflector. The rotating sub-reflector creates a virtual phase center that rotates about an axis to produce a synthetic circular array with a diameter of 120?. The main reflector redirects the beams from each of these virtual phase centers to overlap and illuminate the scene over a wide field of view. The proposed system can reduce the image acquisition time to the order of milliseconds/seconds which makes real-time SAR imaging a practical alternative to MIMO and phased arrays at millimeter-wave and sub-millimeter-wave frequencies.

Abstract: An embodiment of an apparatus comprises one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree, and circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits. Other embodiments are disclosed and claimed.

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation.

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation.