Abstract: A power on reset circuit including an inverter powered by a first power domain, the inverter including a data input coupled to a power rail of a second power domain; logic circuitry coupled with an output of the inverter, the logic circuitry having a control signal output; and wherein, during a power up operation, the first power domain powers up before the second power domain powers up. Upon power up of the first power domain, the inverter can output a high signal to the logic circuitry and output a low signal to the logic circuitry in response to power up of the second power domain. The logic circuitry is further configured to output a first value for a control signal in response to the first power domain powering up and configured to output a second value for the control signal in response to the second power domain powering up.