Abstract: This disclosure introduces a mapping for creating good Doppler detection capable radar codes. The mapping transfers an existing digital radar code to the warped frequency domain by expressing the code elements as magnitudes and phases of selected frequencies. These frequencies are equispaced in the warped frequency domain to preserve the code's sidelobes after mapping. The frequency warping function may convert the multiplicative Doppler shift into an additive shift of the code pattern in the warped frequency domain, which allows Doppler shift detection.

Abstract: In this paper, binary stackers and counters are presented. In an embodiment, a counter uses 3-bit stacking circuits which group T bits together, followed a symmetric method to combine pairs of 3-bit stacks into 6-bit stacks. The bit stacks are then converted to binary counts, producing 6:3 and 7:3 Counter circuits with no XOR gates on the critical path. This avoids of XOR gates results in faster designs with efficient power and area utilization. In VLSI simulations, the presently-disclosed counters were 30% faster and at consumed at least 20% less power than existing parallel counters. Additionally, using the presently-disclosed counter in existing Counter Based Wallace tree multiplier architectures reduce latency and improves efficiency in term of power-delay product for 64-bit and 128-bit multipliers.

Abstract: This disclosure introduces a mapping for creating good Doppler detection capable radar codes. The mapping transfers an existing digital radar code to the warped frequency domain by expressing the code elements as magnitudes and phases of selected frequencies. These frequencies are equispaced in the warped frequency domain to preserve the code's sidelobes after mapping. The frequency warping function may convert the multiplicative Doppler shift into an additive shift of the code pattern in the warped frequency domain, which allows Doppler shift detection.

Abstract: In this paper, binary stackers and counters are presented. In an embodiment, a counter uses 3-bit stacking circuits which group the T bits together, followed by a symmetric method to combine pairs of 3-bit stacks into 6-bit stacks. The bit stacks are then converted to binary counts, producing 6:3 and 7:3 Counter circuits with no XOR gates on the critical path. This avoidance of XOR gates results in faster designs with efficient power and area utilization. In VLSI simulations, the presently-disclosed counters were 30% faster and at consumed at least 20% less power than existing parallel counters. Additionally, using the presently-disclosed counter in existing Counter Based Wallace tree multiplier architectures reduces latency and improves efficiency in terms of power-delay product for 64-bit and 128-bit multipliers.

Abstract: The subject matter described in this specification can be embodied in a method that includes partitioning a received signal into a sequence of two or more segments. For a given segment in the sequence, the method includes calculating a set of frequency domain coefficients corresponding to the given segment, and identifying local peaks in the set of frequency domain coefficients by applying a threshold. The method also includes providing a multi-dimensional histogram from a plurality of peaks identified from multiple segments, wherein the multi-dimensional histogram jointly represents frequencies and coefficient values corresponding to each of the plurality of identified peaks.

Abstract: The subject matter described in this specification can be embodied in a method that includes partitioning a received signal into a sequence of two or more segments. For a given segment in the sequence, the method includes calculating a set of frequency domain coefficients corresponding to the given segment, and identifying local peaks in the set of frequency domain coefficients by applying a threshold. The method also includes providing a multi-dimensional histogram from a plurality of peaks identified from multiple segments, wherein the multi-dimensional histogram jointly represents frequencies and coefficient values corresponding to each of the plurality of identified peaks.

Abstract: A method for generating partial sums from at least four multiple-digit sequences in a computing device includes partitioning the multiple-digit sequences into at least a first set of multiple-digit sequences and a second set of multiple-digit sequences. The method also includes generating at least one auxiliary set of multiple-digit sequences. The auxiliary set includes digits copied from respective digit positions of multiple-digit sequences in the first and second sets. The method further includes replacing the copied digits in the first and second sets by zeros to obtain a first altered set and a second altered set, respectively, of multiple-digit sequences each comprising multiple segments separated by the replaced zeros.

Abstract: A method for generating partial sums from at least four multiple-digit sequences in a computing device includes partitioning the multiple-digit sequences into at least a first set of multiple-digit sequences and a second set of multiple-digit sequences. The method also includes generating at least one auxiliary set of multiple-digit sequences. The auxiliary set includes digits copied from respective digit positions of multiple-digit sequences in the first and second sets. The method further includes replacing the copied digits in the first and second sets by zeros to obtain a first altered set and a second altered set, respectively, of multiple-digit sequences each comprising multiple segments separated by the replaced zeros.

Abstract: The present solution provides methods and systems for realizing hardware efficient mismatched filters for pulse compression codes. For pulse compression codes with sufficiently small sidelobe structures, such as in the cases of odd length Barker codes, the proposed filters require a small number of adders and multipliers per output. This translates to significantly reduced chip-area and lower power consumption when implemented on a chip. In one aspect, the present application features a method for suppressing an undesired part of a waveform. The method includes filtering a signal via a filter. In one embodiment, the signal includes an expected waveform that can be represented as a sum of the desired part and the undesired part. The impulse response of the filter can be represented a sum of the desired part and a negative of the undesired part.

Abstract: The present solution provides methods and systems for realizing hardware efficient mismatched filters for pulse compression codes. For pulse compression codes with sufficiently small sidelobe structures, such as in the cases of odd length Barker codes, the proposed filters require a small number of adders and multipliers per output. This translates to significantly reduced chip-area and lower power consumption when implemented on a chip. In one aspect, the present application features a method for suppressing an undesired part of a waveform. The method includes filtering a signal via a filter. In one embodiment, the signal includes an expected waveform that can be represented as a sum of the desired part and the undesired part. The impulse response of the filter can be represented a sum of the desired part and a negative of the undesired part.

Abstract: Very efficient sidelobe suppression of Barker codes is achieved through the use of a mismatched filter, which is comprised of a conventional matched filter cascaded with a computationally efficient filter based on multiplicative expansion. Several constant parameters are introduced in the terms of the expansion and are optimized to improve the performance of the filter. Optimized mismatched filters for length 13, 11, 7 and 5 Barker codes are presented. For each of these codes, filters with one, two and three stages are studied. The technique is extended to compound Barker codes based on their representation in a factored form in the z-domain. Hardware requirements for the filters discussed in the disclosure are also presented.

Abstract: A new class of biphase complementary code sets is proposed. Individual codes in each set have peak sidelobes of unity magnitude. The individual codes could have gaps of zeros but they are interlaced together without gaps in the final scheme. A number of such codes, as introduced here, use Barker codes as building blocks with additional elements from {+1,?1,0}. The main drawback of regular complementary codes longer than 4 is that they have sidelobe magnitude greater than unity. In the presence of frequency selective fading, inexact sidelobe cancellation results in non-zero sidelobes at the output. These sidelobes are minimized by using sets with individual codes that have peak sidelobes of unity magnitude. The constituent codes are transmitted at different frequencies. They are transmitted in parallel or using an appropriate combination of frequency division multiplexing (FDM) and time division multiplexing (TDM) such that the final transmission scheme is free of gaps.

Abstract: Very efficient sidelobe suppression of Barker codes is achieved through the use of a mismatched filter, which is comprised of a conventional matched filter cascaded with a computationally efficient filter based on multiplicative expansion. Several constant parameters are introduced in the terms of the expansion and are optimized to improve the performance of the filter. Optimized mismatched filters for length 13, 11, 7 and 5 Barker codes are presented. For each of these codes, filters with one, two and three stages are studied. The technique is extended to compound Barker codes based on their representation in a factored form in the z-domain. Hardware requirements for the filters discussed in the disclosure are also presented.