Patents by Inventor Adnan Khaleel

Adnan Khaleel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reducing probe traffic in multiprocessor systems
    Patent number: 7296121
    Abstract: A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information. The probe filtering information is representative of states associated with selected ones of the cache memories.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: November 13, 2007
    Assignee: Newisys, Inc.
    Inventors: Eric Morton, Rajesh Kota, Adnan Khaleel, David B. Glasco
  • Reducing probe traffic in multiprocessor systems
    Publication number: 20070055826
    Abstract: A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information. The probe filtering information is representative of states associated with selected ones of the cache memories.
    Type: Application
    Filed: October 15, 2004
    Publication date: March 8, 2007
    Inventors: Eric Morton, Rajesh Kota, Adnan Khaleel, David Glasco
  • Histogram performance counters for use in transaction latency analysis
    Publication number: 20050177344
    Abstract: Methods and apparatus are described for measuring latency in computer systems. A computer system includes a processor, memory, and I/O. The processor is operable to initiate transactions involving the memory and the I/O. The computer system further includes a latency counter operable to measure a latency for each of selected ones of the transactions. The system also includes a plurality of histogram counters. Each histogram counter is operable to count the latencies corresponding to an associated latency range.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 11, 2005
    Inventor: Adnan Khaleel