Abstract: A method of producing a large-scale integrated MOS field effect transistor circuit which includes forming p and n-doped troughs, respectively, in a silicon substrate to accommodate respective n and p-channel transistors, introducing appropriate dopant atoms into the troughs by repeated ion implantations to adjust various transistor cutoff voltages, and masking the various ion implantations with photo resist structures and/or with silicon oxide and silicon nitride structures, respectively, and which includes forming source/drain and gate areas as well as forming intermediate and insulation oxide and a strip conductor plane in accordance with conventional MOS technology methods includes the steps of: applying a total-area oxide film having a first film thickness (d1.sub.

Abstract: Complementary MOS field effect transistor circuits are produced in silicon gate technology, with the method steps up to the structuring of the gate electrode being executed in a known manner. Both source/drain implantations (FIG. 3, 8 and FIG. 5, 10) occur with only one mask (7a). This mask (7a), which is composed of silicon nitride, is utilized for the source/drain implantation 8 of the n-channel transistors (9). The source/drain implantation (10) for the p-channel transistors (11) occurs without a mask and the oxide layer thickness, d.sub.6, over the source/drain regions of the n-channel transistors (9) functions as a masking layer. An advantage of this process sequence is that switched capacitor structures (FIG. 6, 5b, 12) can be simultaneously produced whereby the oxide layer thickness, d.sub.4, over the polysilicon-1 level (5a, 5b) determines the thickness of the insulating layer, d.sub.cox, of the capacitor structures (5b, 12).

Abstract: Reprogrammable semiconductor read-only memory with memory cells of the floating-gate type, including an additional potential carrier for each memory cell for capacitively coupling a further potential to the floating gate.

Abstract: A method of producing a monolithically integrated two-transistor memory cell, including a silicon crystal for accommodating the memory cell, a first MOS field effect transistor having a current-carrying channel and both a control gate and a floating gate disposed between the control gate and surface of the crystal, a second MOS field effect transistor having a current-carrying channel and a control gate, an SiO.sub.2 film supporting the gates, a doped polycrystalline silicon layer deposited on the SiO.sub.2 film, the control gates and the floating gate being formed from the doped polycrystalline silicon layer, and an erase area for the floating gate, the improvement which includes covering a part of the silicon crystal intended for the memory cell with an SiO.sub.2 film, forming a part of the gate oxide of the first MOS field effect transistor, forming a window through the SiO.sub.