Abstract: A semiconductor device comprises semiconductor substrate including vertical transistor and with dopants of a first type. Each transistor cell of transistor has body region formed in substrate and with dopants of second type. The body regions form first pn-junctions with substrate. A first well region is formed in substrate and with dopants of a second type forming a second pn-junction with substrate. Switch connects this first well region to body regions. A second well region is formed in the substrate and with dopants of a second type to form third pn-junction with substrate. Detection circuit is integrated in the second well region and to detect whether the first pn-junctions are reverse biased. The switch connects or disconnects the first well region(s) and the body regions of the transistor cell, and is opened, when the first pn-junctions are reverse biased, and closed, when the first pn-junctions are not reverse biased.

Abstract: A semiconductor device comprises semiconductor substrate including vertical transistor and with dopants of a first type. Each transistor cell of transistor has body region formed in substrate and with dopants of second type. The body regions form first pn-junctions with substrate. A first well region is formed in substrate and with dopants of a second type forming a second pn-junction with substrate. Switch connects this first well region to body regions. A second well region is formed in the substrate and with dopants of a second type to form third pn-junction with substrate. Detection circuit is integrated in the second well region and to detect whether the first pn-junctions are reverse biased. The switch connects or disconnects the first well region(s) and the body regions of the transistor cell, and is opened, when the first pn-junctions are reverse biased, and dosed, when the first pn-junctions are not reverse biased.

Abstract: Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit.

Abstract: Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which drive a pair of adjacent wires with differential current pulses that are received by a differential receiver which may be put in a low power state between transmissions.

Abstract: An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which drive a pair of adjacent wires with differential current pulses that are received by a differential receiver which may be put in a low power state between transmissions.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A semiconductor device may include a borderless logic array and area I/Os. The logic array may comprise a repeating core, and at least one of the area I/Os may be a configurable I/O. Furthermore, the configurable I/O may comprise at least one metal layer that is the same for all I/O configurations.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.