Abstract: A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.

Abstract: A method for protecting a circuit from a high energy pulse includes placing a PPTC resistive element in series with the circuit and placing an energy pulse clamping semiconductor diode in shunt across the circuit and further includes forming the diode to have: a substrate with carriers of a first type of conductivity in a first, high concentration level (e.g. n++), a first major face and a second major face opposite to the first major face; a layer of semiconductor material having carriers of the first type of conductivity in a second concentration level lower than the first level (e.g. n+), and an outer surface; a region formed at an outer surface having carriers of a second type of conductivity in a third concentration level (e.g. p+); at least one cell having carriers of the second type of conductivity in a fourth concentration level greater than the third concentration level (e.g. p++); and, a cathode electrode and an anode electrode.

Abstract: A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.

Abstract: An energy pulse clamping semiconductor diode includes a substrate having carriers of a first type of conductivity in a first, high concentration level (e.g. n++), a first major face and a second major face opposite to the first major face; a layer of semiconductor material having carriers of the first type of conductivity in a second concentration level lower than the first level (e.g. n+), and having an outer surface; a region formed at an outer surface having carriers of a second type of conductivity in a third concentration level (e.g. p+); at least one cell having carriers of the second type of conductivity in a fourth concentration level greater than the third concentration level (e.g. p++); a cathode electrode and an anode electrode. The diode is most preferably included in an overvoltage protection circuit including a PPTC resistor in series with the cathode electrode and thermally coupled to the diode.

Abstract: A protection circuit for use with a charger and a chargeable element, such as a rechargeable lithium ion battery, comprises a shunt regulator having a threshold ON voltage coupled in parallel across the chargeable element, and a temperature-dependent resistor, e.g., a positive temperature coefficient device, coupled in series between the charger and the chargeable element. The temperature dependent resistor is thermally and electrically coupled to the shunt regulator, wherein the first variable resistor limits current flowing through the shunt regulator if the current reaches a predetermined level less than that which would cause failure of the regulator, due to ohmic heating of the regulator.

Abstract: A protection circuit for use with a charger and a chargeable element, such as a rechargeable lithium ion battery, comprises a shunt regulator having a threshold ON voltage coupled in parallel across the chargeable element, and a temperature-dependent resistor, e.g., a positive temperature coefficient device, coupled in series between the charger and the chargeable element. The temperature dependent resistor is thermally and electrically coupled to the shunt regulator, wherein the first variable resistor limits current flowing through the shunt regulator if the current reaches a predetermined level less than that which would cause failure of the regulator, due to ohmic heating of the regulator.

Abstract: A protection circuit for use with a charger and a chargeable element, such as a rechargeable lithium ion battery, comprises a shunt regulator having a threshold ON voltage coupled in parallel across the chargeable element, and a temperature-dependent resistor, e.g., a positive temperature coefficient device, coupled in series between the charger and the chargeable element. The temperature dependent resistor is thermally and electrically coupled to the shunt regulator, wherein the first variable resistor limits current flowing through the shunt regulator if the current reaches a predetermined level less than that which would cause failure of the regulator, due to ohmic heating of the regulator.

Abstract: A protection circuit for use with a charger and a chargeable element, such as a rechargeable lithium ion battery, comprises a shunt regulator having a threshold ON voltage coupled in parallel across the chargeable element, and a temperature-dependent resistor, e.g., a positive temperature coefficient device, coupled in series between the charger and the chargeable element. The temperature dependent resistor is thermally and electrically coupled to the shunt regulator, wherein the first variable resistor limits current flowing through the shunt regulator if the current reaches a predetermined level less than that which would cause failure of the regulator, due to ohmic heating of the regulator.

Abstract: A protection circuit for use with a charger and a chargeable element, such as a rechargeable lithium ion battery, comprises a shunt regulator having a threshold ON voltage coupled in parallel across the chargeable element, and a temperature-dependent resistor, e.g., a positive temperature coefficient device, coupled in series between the charger and the chargeable element. The temperature dependent resistor is thermally and electrically coupled to the shunt regulator, wherein the first variable resistor limits current flowing through the shunt regulator if the current reaches a predetermined level less than that which would cause failure of the regulator, due to ohmic heating of the regulator.

Abstract: A protection circuit for use with a charger and a chargeable element, such as a rechargeable lithium ion battery, comprises a shunt regulator having a threshold ON voltage coupled in parallel across the chargeable element, and a temperature-dependent resistor, e.g., a positive temperature coefficient device, coupled in series between the charger and the chargeable element. The temperature dependent resistor is thermally and electrically coupled to the shunt regulator, wherein the first variable resistor limits current flowing through the shunt regulator if the current reaches a predetermined level less than that which would cause failure of the regulator, due to ohmic heating of the regulator.

Abstract: A process for manufacturing a DMOS transistor in accordance with the present invention includes the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of polycrystalline silicon (16) is formed on the gate insulation layer. A first mask (18) is used to define the polycrystalline silicon gate. A layer of silicon dioxide (20) is then formed on the polycrystalline silicon gate. A second photolithographic mask (22) is formed on the wafer. The deep body region is then formed. Thereafer, portions of the gate insulation layer not covered by the polycrystalline silicon gate are removed. The P type body region (26) and N+ source region (28) are then formed having a lateral extent defined by the edge of the polycrystalline silicon gate. A conductive layer 30 l is formed on the wafer and photolithographically patterned. A passivation layer 34 is then formed on the wafer.

Abstract: A process for manufacturing a DMOS transistor in accordance with the present invention includes the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of polycrystalline silicon (16) is formed on the gate insulation layer. A first mask (18) is used to define the polycrystalline silicon gate (16e, 16f). A layer of silicon dioxide (20) is then formed on the gate. A second mask (22) defines the gate contact region (window 22a)) as well as where a deep body region (24) is to be formed (window 14a)). Portions of the gate insulation layer not covered by the gate are subsequently removed. The P type body region (26) and N+ source region (28) are then formed having a lateral extent defined by the edge of the gate. A conductive layer 30 is patterned, thereby leaving a gate contact and a source and body contact. A passivation layer 34 is then patterned, thereby defining bonding pads. Of importance, the above-described process uses only 4 photolithographic masking steps.

Abstract: Energy-saving circuitry for a rapid-start fluorescent lighting system includes a reactance-modifying capacitor coupled in series with first and second fluorescent lamps and includes a filament switch which is operative to conduct filament heating current during starting of the first lamp. The filament switch is coupled between filaments at opposite ends of the first fluorescent lamp and triggers to a low impedance state in response to the lamp starting voltage. A capacitor bypass switch can be coupled in parallel with the reactance-modifying capacitor to reduce the impedance of the series circuit during lamp starting.