Abstract: Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.

Abstract: The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.

Abstract: Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.

Abstract: The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.

Abstract: Automated verification methodology parsing scripts auto generate testbench hardware design language, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e.g., auto-generated rules, in the testbench.

Abstract: As described herein the automated verification methodology parsing scripts auto generate test bench hardware design langaue, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e.g., auto-generated rules, in the test bench.

Abstract: A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.

Abstract: An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses.

Abstract: A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system.

Abstract: A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system.

Abstract: An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register. An automatic wake-up mechanism may also be provided to keep the array active during extended periods of non-use.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A method and an apparatus are disclosed for converting error syndromes of an error-correcting code to pointers which identify the positions of the erroneous bits. Each syndrome is converted by a plurality of hashing functions into a plurality of hash words, which in turn are used to address a plurality of read-only stores. The outputs of the read-only stores are logically combined to obtain the respective error pointer. A preferred embodiment uses three hashing functions (41, 43, 45) and three read-only stores (53, 55, 57) and combines their outputs by an Exclusive-Or function (59). The storage capacity and the processing time required for syndrome-to-error pointer conversion are reduced by the disclosed scheme.