Patents by Inventor Adrian Earle
Adrian Earle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929113Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.Type: GrantFiled: December 2, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Atul Katoch, Adrian Earle
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Publication number: 20230098852Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.Type: ApplicationFiled: December 2, 2022Publication date: March 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Atul Katoch, Adrian Earle
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Patent number: 11521673Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.Type: GrantFiled: February 15, 2021Date of Patent: December 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Atul Katoch, Adrian Earle
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Publication number: 20210166750Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.Type: ApplicationFiled: February 15, 2021Publication date: June 3, 2021Inventors: Atul Katoch, Adrian Earle
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Patent number: 10923182Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.Type: GrantFiled: August 20, 2019Date of Patent: February 16, 2021Inventors: Atul Katoch, Adrian Earle
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Patent number: 10878853Abstract: A memory device includes a controller connected to first, second, third and fourth switches and configured to selectively operate the switches to connect first and second source voltage input terminals to a memory based on a desired current level required for the memory array.Type: GrantFiled: July 22, 2019Date of Patent: December 29, 2020Inventor: Adrian Earle
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Publication number: 20200075085Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.Type: ApplicationFiled: August 20, 2019Publication date: March 5, 2020Inventors: Atul Katoch, Adrian Earle
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Publication number: 20200043531Abstract: A memory device includes a controller connected to first, second, third and fourth switches and configured to selectively operate the switches to connect first and second source voltage input terminals to a memory based on a desired current level required for the memory array.Type: ApplicationFiled: July 22, 2019Publication date: February 6, 2020Inventor: Adrian Earle
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Patent number: 9940988Abstract: A method of controlling a wordline by a driver decoder circuit includes generating a first control signal having a first logically high level and a first logically low level, and generating a second control signal having a second logically high level when the first control signal has the first logically high level and a second logically low level when the first control signal has the first logically low level. The first logically high level is different from the second logically high level, and the first logically low level is different from the second logically low level. The method includes coupling the wordline to a first node having a first voltage value in response to the first control signal having the first logically low level and decoupling the wordline from a second node having a second voltage value in response to the second control signal having the second logically low level.Type: GrantFiled: April 28, 2016Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Adrian Earle, Atul Katoch
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Publication number: 20160240235Abstract: A method of controlling a wordline by a driver decoder circuit includes generating a first control signal having a first logically high level and a first logically low level, and generating a second control signal having a second logically high level when the first control signal has the first logically high level and a second logically low level when the first control signal has the first logically low level. The first logically high level is different from the second logically high level, and the first logically low level is different from the second logically low level. The method includes coupling the wordline to a first node having a first voltage value in response to the first control signal having the first logically low level and decoupling the wordline from a second node having a second voltage value in response to the second control signal having the second logically low level.Type: ApplicationFiled: April 28, 2016Publication date: August 18, 2016Inventors: Adrian EARLE, Atul KATOCH
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Patent number: 9355697Abstract: A circuit includes a first transistor and a second transistor of a first type. The circuit further includes a first transistor of a second type. A first first-type drain is coupled to a second first-type source. A first first-type source is configured to have a first voltage value. A first first-type gate is configured to have a first control signal. A second first-type drain is configured to serve as a wordline. A second first-type gate is configured to have a second voltage value. A first second-type source is configured to have a third voltage value. A first second-type gate is configured to have a second control signal. The first transistor and the second transistor of the first type are configured to provide the first voltage value for the wordline. The first transistor of the second-type is configured to provide the third voltage value the wordline.Type: GrantFiled: October 5, 2012Date of Patent: May 31, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Adrian Earle, Atul Katoch
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Patent number: 9224446Abstract: A memory circuit includes first and second word lines, a plurality of memory cells and a timing controller. Each memory cell includes a first access port and a second access port. The first access port is coupled to the first word line and configured to be enabled by a first word line signal on the first word line. The second access port is coupled to the second word line and configured to be enabled by a second word line signal on the second word line. The timing controller is configured to receive a timing select signal and to control a time delay between the first word line signal and the second word line signal to be different in response to different first and second states of the timing select signal.Type: GrantFiled: October 31, 2012Date of Patent: December 29, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Adrian Earle
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Publication number: 20140119148Abstract: A memory circuit includes first and second word lines, a plurality of memory cells and a timing controller. Each memory cell includes a first access port and a second access port. The first access port is coupled to the first word line and configured to be enabled by a first word line signal on the first word line. The second access port is coupled to the second word line and configured to be enabled by a second word line signal on the second word line. The timing controller is configured to receive a timing select signal and to control a time delay between the first word line signal and the second word line signal to be different in response to different first and second states of the timing select signal.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Adrian EARLE
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Patent number: 8201033Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.Type: GrantFiled: June 30, 2011Date of Patent: June 12, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi
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Publication number: 20110258515Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi
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Patent number: 7996734Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.Type: GrantFiled: July 9, 2010Date of Patent: August 9, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi
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Publication number: 20100281302Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.Type: ApplicationFiled: July 9, 2010Publication date: November 4, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi
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Patent number: 7779334Abstract: An error correction code system for a memory having parity columns of a memory array located within the memory array is provided. The parity columns are grouped together or distributed throughout the memory array. An embodiment includes a multiplexor circuit for selectively coupling only parity bits stored in the parity memory array to I/O circuitry, bypassing ECC logic circuitry and allowing the parity columns to be directly accessible, in a direct access mode or for selectively coupling the parity bits to ECC logic circuitry in an ECC mode.Type: GrantFiled: June 25, 2007Date of Patent: August 17, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi
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Publication number: 20030160630Abstract: A repeater circuit for detecting and accelerating the transitioning edge of a signal on a bi-directional bus. The repeater includes rising and falling edge detectors for detecting a change in the potential level of the bi-directional bus and does not require logic for determining the direction of propagation of the signal. The edge detectors subsequently activate a drive circuit for accelerating the potential level transition of the signal on the bi-directional bus. A buffer circuit can be placed between the edge detectors and the bi-directional bus to ensure that any transition on the bi-directional bus is an intended signal transition and not a voltage spike.Type: ApplicationFiled: February 27, 2002Publication date: August 28, 2003Inventor: Adrian Earle