Abstract: A method for eliminating an arc driven by at least one phase voltage source of a converter circuit is disclosed. The converter circuit can include a converter unit and an energy storage circuit, wherein the at least one phase voltage source can be connected on an AC voltage side of the converter unit, and the converter unit can have a plurality of actuable power semiconductor switches. The method can include monitoring a state variable of the converter circuit for a predeterminable threshold value of the state variable to detect an arc, and actuating at least one of the plurality of actuable power semiconductor switches of the converter unit upon detecting a discrepancy between the state variable and the predeterminable threshold value.

Abstract: A method for eliminating an arc driven by at least one phase voltage source of a converter circuit is disclosed. The converter circuit can include a converter unit and an energy storage circuit, wherein the at least one phase voltage source can be connected on an AC voltage side of the converter unit, and the converter unit can have a plurality of actuable power semiconductor switches. The method can include monitoring a state variable of the converter circuit for a predeterminable threshold value of the state variable to detect an arc, and actuating at least one of the plurality of actuable power semiconductor switches of the converter unit upon detecting a discrepancy between the state variable and the predeterminable threshold value.

Abstract: A converter circuit arrangement for increasing an alternating voltage is specified, which has a converter (2), which is designed as an inverter, a filter circuit (3) being connected to alternating voltage terminals (8.1, 8.2) of the converter (2) and the filter circuit (3) including at least one partial filter circuit (4). Furthermore, the partial filter circuit (4) is designed in such a way that a converter output current (IU) flowing in the partial filter circuit (4) is leading in time with respect to a partial filter output voltage (UF) present at load terminals (5, 6) of the partial filter circuit (4) and a converter output voltage (UU) present at the alternating voltage terminals (8.1, 8.2) is limited to a specifiable value (|UUb|).