Patents by Inventor Adrian H. W. Hoodless

Adrian H. W. Hoodless has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4682086
    Abstract: A CRT display system providing a raster pattern has digital means 30, 31, 32 to drive a DAC 34. In response, there are supplied analogue signals, on a line 37. There are also provided pulse generating means 90 controlled by the digital means, and integrating means comprising two integrators. Each integrator is connected individually to an X deflection plate 14 of the CRT, and comprises an amplifier and a feedback capacitor. One capacitor C2 is charged by negative-going pulses, and the other capacitor C2' is charged by positive-going pulses, until the pulses are removed, when the required ramps are applied to the deflection plates. Then a current flows through a transistor T7, and is controlled by the DAC output on the line 37. Hence, the waveforms applied to the deflection plates cause distortion of the raster pattern otherwise obtained, to be corrected, the DAC output representing a function comprising the inverse of the function representing the distortion.
    Type: Grant
    Filed: September 14, 1984
    Date of Patent: July 21, 1987
    Assignee: Ferranti, plc
    Inventors: Andrew M. Mallinson, Adrian H. W. Hoodless
  • Patent number: 4583118
    Abstract: A circuit for converting a TV receiver to operate in accordance with the system associated with received signals, there being either F or F' scan lines in a field, with F<F', includes a counter driven by pulses each representative of one end of a raster scan line, and having M stages, with F and F'<M<2F and 2F'. There is also means to preload the counter selectively with a count of R or R', where (M-2R)=F and (M-2R')=F'. Wide window means detects when a field sync pulse is within a window including the (M-R)th and (M-R') stages, and, in response, the counter, initially, is preloaded with R'. Decision logic means then detects whether a field sync pulse occurs after the Kth stage, with K=M-[R+R']/2, when R' is continued to be preload; or occurs before the Kth stage, when R subsequently is preloaded; and the required TV receiver conversion is completed.
    Type: Grant
    Filed: September 14, 1984
    Date of Patent: April 15, 1986
    Assignee: Ferranti, PLC
    Inventors: Andrew M. Mallinson, Adrian H. W. Hoodless