Abstract: A GNSS receiver comprises a memory interface and a vector processor. The vector processor is configured to: receive, via the memory interface, an array comprising a plurality of correlation results stored in a memory, each correlation result associated with a respective combination of possible receiver parameters for the GNSS receiver; process the array to identify a subset of the correlation results in the array; and retain, in the memory, the identified subset and discard, from the memory, those correlation results of the plurality of correlation results not in the identified subset.

Abstract: A technique for efficient calling of functions on a processor generates an executable program having a function call by analysing an interface for the function that defines an argument expression and an internal value used solely within the function, and an argument declaration defining an argument value to be provided to the function when the program is run. A data structure is generated including the internal value and a resolved argument value derived from the argument expression and the argument value. A single instruction is encoded in the program to utilise the data structure. When the program is executed on a processor, the single instruction causes the processor to load the argument value and internal value from the data structure into registers in the processor, prior to evaluating the function. The function can then be executed without further register loads being performed.

Abstract: Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.

Abstract: A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm.

Abstract: Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.

Abstract: A GNSS correlator comprises a buffer and a processing unit. The buffer is configured to store input data representing sample values of a GNSS signal captured over a pre-defined time window. The processing unit is configured to receive one or more correlation parameters in a control signal, and, in a first pass, read the input data from the buffer and perform a first correlation operation on the input data, and, in a second pass, re-read the same input data from the buffer and perform a second correlation operation on the same input data, wherein the second correlation operation is different to the first correlation operation.

Abstract: A ranging code correlation function detection system for use in a global navigation satellite system (GNSS) receiver includes a correlation block to correlate a digitized GNSS signal (e.g. at or above a critical sampling rate) with a corresponding ranging code at each of a plurality of different offsets from a current estimate of a code delay to generate a plurality of correlation data points; an interpolation filter configured to generate at least one estimated correlation data point that lies between two of the correlation data points based on the current estimate of the code delay. In some cases the ranging code correlation function detection system may also include a discriminator block configured to generate an updated estimate of the code delay based on the at least one estimated correlation data point.

Abstract: Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.

Abstract: A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm.

Abstract: A Gaussian frequency shift keying (GFSK) detector for decoding a GFSK signal. The detector includes: a multi-symbol detector and a Viterbi decoder. The multi-symbol detector is configured to: receive a series of samples representing a received GFSK modulated signal; and generate, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, a plurality of soft decision values that indicate the probability that the N-symbol sequence is each possible N-symbol pattern, wherein N is an integer greater than or equal to two. The Viterbi decoder is configured to estimate each N-symbol sequence using a Viterbi decoding algorithm wherein the soft decision values for the N-symbol sequence are used as branch metrics in the Viterbi decoding algorithm.

Abstract: A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm.

Abstract: An IQ amplitude balance estimator is described herein which uses a positive frequency mixer to generate two outputs. The first output is the standard output from a positive frequency mixer and the second output corresponds to a spectrum inverted output from a negative frequency mixer. The second output is generated, however, using the same partial products as the first output and no negative frequency mixer is used. An IQ amplitude imbalance metric is generated by taking the real part of the output from correlation logic which performs a correlation of the two outputs from the mixer. This metric may then be used in a closed loop to compensate for any IQ amplitude imbalance.

Abstract: A GNSS receiver comprises a memory interface and a vector processor. The vector processor is configured to: receive, via the memory interface, an array comprising a plurality of correlation results stored in a memory, each correlation result associated with a respective combination of possible receiver parameters for the GNSS receiver; process the array to identify a subset of the correlation results in the array; and retain, in the memory, the identified subset and discard, from the memory, those correlation results of the plurality of correlation results not in the identified subset.

Abstract: A GNSS receiver comprises a memory interface, at least one front end processor and a correlator. The at least one front end processor is configured to receive a GNSS signal, generate a plurality of data samples, form a set from the data samples, and write the set to a memory via the memory interface. The correlator is configured to retrieve from the memory, via the memory interface, a first batch of data for processing, the first batch of data comprising data samples from at least a portion of the set, process the first batch of data, and subsequent to retrieving the first batch of data, retrieve from the memory, via the memory interface, a second batch of data for processing, the second batch of data comprising different data samples from those in the first batch.

Abstract: A GNSS receiver is configured to operate in a first mode and in a second mode. The GNSS receiver comprises a processor clock, a memory interface, and a correlator. The processor clock is controllable to operate at a first rate and a second rate, wherein the first clock rate is different to the second clock rate. The correlator is configured to retrieve from a memory, via the memory interface, at least a portion of a set of captured data samples, perform one or more correlation operations on the data samples to generate at least one correlation result, wherein the correlator is configured to generate the at least one correlation result at a rate determined by the processor clock. When the GNSS receiver is operating in the first mode, the correlator is clocked at the first clock rate and, when the GNSS receiver is operating in the second mode, the correlator is clocked at a second clock rate.

Abstract: A GNSS receiver comprises an input, at least one front end processor, and an interference mitigation unit. The input is configured to receive from a wireless communication module a control signal comprising timing information, the timing information indicating one or more transmission times during which the wireless communication module wirelessly transmits data. The at least one front end processor is configured to capture a set of data samples from a received GNSS signal and store the data samples in a memory, each sample captured at a corresponding sample time. The interference mitigation unit is configured to configured to identify data samples of the set of data samples that have a sample time that corresponds with one or more transmission times as candidate samples for interference.

Abstract: A GNSS correlator comprises a buffer and a processing unit. The buffer is configured to store input data representing sample values of a GNSS signal captured over a pre-defined time window. The processing unit is configured to receive one or more correlation parameters in a control signal, and, in a first pass, read the input data from the buffer and perform a first correlation operation on the input data, and, in a second pass, re-read the same input data from the buffer and perform a second correlation operation on the same input data, wherein the second correlation operation is different to the first correlation operation.

Abstract: A GNSS receiver comprises a memory interface, one more front end processors, a correlator and a computation unit. The one more front end processors are configured to store, using the memory interface, in a first portion of a shared memory, a set of captured data samples of a received GNSS signal. The correlator is configured to retrieve, using the memory interface, at least a portion of the data samples from the first portion, generate a plurality of correlation results, each correlation result indicating a degree of correlation between the retrieved data samples and a ranging code of a plurality of ranging codes, and store, using the memory interface, the plurality of correlation results in a second portion of the shared memory.

Abstract: A technique for efficient calling of functions on a processor generates an executable program having a function call by analysing an interface for the function that defines an argument expression and an internal value used solely within the function, and an argument declaration defining an argument value to be provided to the function when the program is run. A data structure is generated including the internal value and a resolved argument value derived from the argument expression and the argument value. A single instruction is encoded in the program to utilise the data structure. When the program is executed on a processor, the single instruction causes the processor to load the argument value and internal value from the data structure into registers in the processor, prior to evaluating the function. The function can then be executed without further register loads being performed.

Abstract: A Gaussian frequency shift keying (GFSK) detector for decoding a GFSK signal. The detector includes: a multi-symbol detector and a Viterbi decoder. The multi-symbol detector is configured to: receive a series of samples representing a received GFSK modulated signal; and generate, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, a plurality of soft decision values that indicate the probability that the N-symbol sequence is each possible N-symbol pattern, wherein N is an integer greater than or equal to two. The Viterbi decoder is configured to estimate each N-symbol sequence using a Viterbi decoding algorithm wherein the soft decision values for the N-symbol sequence are used as branch metrics in the Viterbi decoding algorithm.