Abstract: Methods and systems for processing image data on a per tile basis in an image sensor pipeline (ISP) are disclosed and may include communicating, to one or more processing modules via control logic circuits integrated in the ISP, corresponding configuration parameters that are associated with each of a plurality of data tiles comprising an image. The ISP may be integrated in a video processing core. The plurality of data tiles may vary in size. A processing complete signal may be communicated to the control logic circuits when the processing of each of the data tiles is complete prior to configuring a subsequent processing module. The processing may comprise one or more of: lens shading correction, statistics, distortion correction, demosaicing, denoising, defective pixel correction, color correction, and resizing. Each of the data tiles may overlap with adjacent data tiles, and at least a portion of them may be processed concurrently.

Abstract: A method and system are provided in which color channel information may be stored in a multimedia processor. The color channel information may comprise information for each of the color filter positions in a color filter pattern. The color channel information may be stored in a plurality of registers, wherein each register may correspond to a color channel. The color channel information may be dynamically stored in the multimedia processor. Based on the color channel information, a color channel may be assigned to each color filter position. The color channel assigned to a color filter position may be one of red, green, blue, white, cyan, yellow, and/or magenta. When an indication of the color filter pattern is received, the assignment may be based on both the color channel information and the received indication. Pixel values associated with the color filter pattern may be processed based on the color channel assignment.

Abstract: Methods and systems for processing image data on a per tile basis in an image sensor pipeline (ISP) are disclosed and may include communicating, to one or more processing modules via control logic circuits integrated in the ISP, corresponding configuration parameters that are associated with each of a plurality of data tiles comprising an image. The ISP may be integrated in a video processing core. The plurality of data tiles may vary in size. A processing complete signal may be communicated to the control logic circuits when the processing of each of the data tiles is complete prior to configuring a subsequent processing module. The processing may comprise one or more of: lens shading correction, statistics, distortion correction, demosaicing, denoising, defective pixel correction, color correction, and resizing. Each of the data tiles may overlap with adjacent data tiles, and at least a portion of them may be processed concurrently.