Patents by Inventor Adrian LIS

Adrian LIS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240413118
    Abstract: A power module is disclosed herein. In one embodiment, the power modules includes a solder repellent structure that adjoins a metallic surface of a substrate outside a perimeter of an electronic component attached to the metallic surface of the substrate and positioned adjacent to one or more sides of the electronic component, the solder repellent structure being configured to repel molten solder. In another embodiment, the power modules includes a solder wetting structure that adjoins a metallic surface of a substrate outside a perimeter of an electronic component attached to the metallic surface of the substrate and positioned adjacent to one or more sides of the electronic component, where excess solder adheres to the solder wetting structure.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 12, 2024
    Inventors: Peter Scherl, Adrian Lis
  • Patent number: 12113000
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: October 8, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ajay Poonjal Pai, Tino Karczewski, Adrian Lis
  • Publication number: 20240304527
    Abstract: A power module includes: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a multi-level lead frame between the first substrate and the second substrate and attached to each of the first part of the patterned first metallization, the first part of the patterned second metallization, the second part of the patterned first metallization, and the second part of the patterned second metallization.
    Type: Application
    Filed: January 30, 2024
    Publication date: September 12, 2024
    Inventors: Dominic Raithel, Adrian Lis, Thomas Schmid
  • Patent number: 12062589
    Abstract: One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: August 13, 2024
    Assignee: Infineon Technologies AG
    Inventors: Adrian Lis, Michael Ledutke
  • Publication number: 20240047429
    Abstract: A power module includes: a first substrate having a patterned first metallization; a second substrate vertically aligned with the first substrate and having a patterned second metallization that faces the patterned first metallization; first vertical power transistor dies having a drain pad attached to a first island of the patterned first metallization and a source pad electrically connected to a first island of the patterned second metallization via first spacers; and second vertical power transistor dies having a source pad electrically connected to the first island of the patterned first metallization via second spacers. A first subset of the second vertical power transistor dies has a drain pad attached to a second island of the patterned second metallization. A second subset of the second vertical power transistor dies has a drain pad attached to a third island of the patterned second metallization. A method of producing the module is described.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Inventors: Adrian Lis, Ewald Guenther, Thomas Schmid
  • Publication number: 20230245968
    Abstract: A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.
    Type: Application
    Filed: January 20, 2022
    Publication date: August 3, 2023
    Inventors: Peter Scherl, Adrian Lis, Christian Neugirg
  • Publication number: 20230223312
    Abstract: A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Christian Neugirg, Adrian Lis, Peter Scherl, Ewald Guenther
  • Publication number: 20230178460
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 8, 2023
    Inventors: Ajay Poonjal Pai, Tino Karczewski, Adrian Lis
  • Publication number: 20230170316
    Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Ivan Nikitin, Adrian Lis, Peter Scherl, Achim Althaus
  • Publication number: 20230054812
    Abstract: A power semiconductor module includes: first and second substrates; at least one power semiconductor die arranged between and thermally coupled to a first side of each substrate, and electrically coupled to the first side of the first substrate; at least one rivet having a first end arranged on and electrically coupled to the first side of the first substrate; and an encapsulant encapsulating the at least one power semiconductor die, the at least one rivet and the substrates. At least parts of a second side of the substrates are exposed from the encapsulant. A second end of the at least one rivet is exposed at the encapsulant and configured to accept a press fit pin such that the at least one power semiconductor die can be electrically contacted from the outside.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 23, 2023
    Inventors: Ajay Poonjal Pai, Tao Hong, Adrian Lis, Oliver Markus Kreiter, Matthias Rose
  • Publication number: 20220415732
    Abstract: A semiconductor module includes: a chip carrier having a first side and a second, opposite side; a semiconductor chip arranged on the first side of the chip carrier; an encapsulation body that encapsulates the semiconductor chip; and at least two external contacts made of a metal or an alloy and arranged next to each other, which are electrically and mechanically connected to the first side of the first chip carrier and protrude laterally out of the encapsulation body. At least one of the external contacts has at least one wing arranged within the encapsulation body and located opposite the other external contact. The wing includes one or more cutouts that are filled with the encapsulation material of the encapsulation body.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 29, 2022
    Inventors: Christoph Liebl, Stefan Schwab, Adrian Lis, Michael Ledutke, Lisa Aschenbrenner
  • Publication number: 20220415745
    Abstract: One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Applicant: Infineon Technologies AG
    Inventors: Adrian LIS, Michael LEDUTKE
  • Publication number: 20220102299
    Abstract: A package is disclosed. In one example, the package comprises an electronic component having a first main surface with an electrically conductive first pad. The first pad has an open notch, and a spacer body mounted on the first pad and bridging at least part of the open notch.
    Type: Application
    Filed: September 28, 2021
    Publication date: March 31, 2022
    Applicant: Infineon Technologies AG
    Inventor: Adrian LIS
  • Patent number: 10479443
    Abstract: Disclosed is an energy harvesting power-assist system and method for human powered light vehicles. The power-assist system comprises a drive mechanism, one or more motor/generators and a high capacity storage device. The system continuously harvests and stores energy which is converted to motion by the motors, providing additional power to the user's pedaling. A controller determines the amount of pedal assist based on a user's preset value, and manages the charge and discharge of the high capacity storage device. As such, the system does not require any other external energy source, and the storage device never needs external charging under the described usage cases.
    Type: Grant
    Filed: November 6, 2016
    Date of Patent: November 19, 2019
    Inventors: Fabian Lis, Gustavo Adrian Lis
  • Publication number: 20180154981
    Abstract: Disclosed is an energy harvesting power-assist system and method for human powered light vehicles. The power-assist system comprises a drive mechanism, one or more motor/generators and a high capacity storage device. The system continuously harvests and stores energy which is converted to motion by the motors, providing additional power to the user's pedaling. A controller determines the amount of pedal assist based on a user's preset value, and manages the charge and discharge of the high capacity storage device. As such, the system does not require any other external energy source, and the storage device never needs external charging under the described usage cases.
    Type: Application
    Filed: November 6, 2016
    Publication date: June 7, 2018
    Inventors: Fabian Lis, Gustavo Adrian Lis
  • Patent number: 7237607
    Abstract: A tubular stabbing protector includes: a plurality of body sections together forming a first opening and a second opening, the first opening sized to be secured over a pin end of an oilfield tubular and the second opening sized to fit over a connection to which the pin end of the tubular is to be engaged and opening away from the first opening; and a releasable lock between each adjacent body section of the plurality of body sections, the releasable lock being automatically releasable when the second opening is fit over the connection to permit the plurality of body sections to separate sufficiently to release the pin end.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: July 3, 2007
    Assignee: Tesco Corporation
    Inventors: Per G. Angman, Gustavo Adrian Lis