Abstract: A power semiconductor module includes: first and second substrates; at least one power semiconductor die arranged between and thermally coupled to a first side of each substrate, and electrically coupled to the first side of the first substrate; at least one rivet having a first end arranged on and electrically coupled to the first side of the first substrate; and an encapsulant encapsulating the at least one power semiconductor die, the at least one rivet and the substrates. At least parts of a second side of the substrates are exposed from the encapsulant. A second end of the at least one rivet is exposed at the encapsulant and configured to accept a press fit pin such that the at least one power semiconductor die can be electrically contacted from the outside.

Abstract: A power module includes: a substrate having a patterned metallization on an electrically insulative body; a plurality of first power semiconductor dies attached to a first metallic island of the patterned metallization; a plurality of second power semiconductor dies attached to a second metallic island of the patterned metallization; a mold compound at least partly embedding the substrate, the first power semiconductor dies, and the second power semiconductor dies; and a multilevel metallic frame partly embedded in the mold compound and disposed over the substrate. The multilevel metallic frame includes a plurality of power terminals exposed at a side of the mold compound that faces away from the patterned metallization and that transition between two or more different levels to electrically interconnect the first power semiconductor dies and the second power semiconductor dies in a half bridge or full bridge configuration.

Abstract: A power module includes: a first substrate having a patterned first metallization; a second substrate vertically aligned with the first substrate and having a patterned second metallization that faces the patterned first metallization; first vertical power transistor dies having a drain pad attached to a first island of the patterned first metallization and a source pad electrically connected to a first island of the patterned second metallization via first spacers; and second vertical power transistor dies having a source pad electrically connected to the first island of the patterned first metallization via second spacers. A first subset of the second vertical power transistor dies has a drain pad attached to a second island of the patterned second metallization. A second subset of the second vertical power transistor dies has a drain pad attached to a third island of the patterned second metallization. A method of producing the module is described.

Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

Abstract: A package is disclosed. In one example, the package comprises an electronic component having a first main surface with an electrically conductive first pad. The first pad has an open notch, and a spacer body mounted on the first pad and bridging at least part of the open notch.

Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

Abstract: A power module includes a substrate, one or more semiconductor dies mounted to the substrate, a first external power connection electrically connected to a first power terminal of at least one of the one or more semiconductor dies, and an encapsulant at least partially encapsulating the first external power connection. A portion of the first external power connection and at least parts of an outer surface of the substrate are exposed from the encapsulant. A heatsink is mounted to the first external power connection.

Abstract: A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

Abstract: A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.

Abstract: A power module is disclosed herein. In one embodiment, the power modules includes a solder repellent structure that adjoins a metallic surface of a substrate outside a perimeter of an electronic component attached to the metallic surface of the substrate and positioned adjacent to one or more sides of the electronic component, the solder repellent structure being configured to repel molten solder. In another embodiment, the power modules includes a solder wetting structure that adjoins a metallic surface of a substrate outside a perimeter of an electronic component attached to the metallic surface of the substrate and positioned adjacent to one or more sides of the electronic component, where excess solder adheres to the solder wetting structure.

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.

Abstract: A power module includes: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a multi-level lead frame between the first substrate and the second substrate and attached to each of the first part of the patterned first metallization, the first part of the patterned second metallization, the second part of the patterned first metallization, and the second part of the patterned second metallization.

Abstract: One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.

Abstract: A power module includes: a first substrate having a patterned first metallization; a second substrate vertically aligned with the first substrate and having a patterned second metallization that faces the patterned first metallization; first vertical power transistor dies having a drain pad attached to a first island of the patterned first metallization and a source pad electrically connected to a first island of the patterned second metallization via first spacers; and second vertical power transistor dies having a source pad electrically connected to the first island of the patterned first metallization via second spacers. A first subset of the second vertical power transistor dies has a drain pad attached to a second island of the patterned second metallization. A second subset of the second vertical power transistor dies has a drain pad attached to a third island of the patterned second metallization. A method of producing the module is described.

Abstract: A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.

Abstract: A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.

Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

Abstract: A power semiconductor module includes: first and second substrates; at least one power semiconductor die arranged between and thermally coupled to a first side of each substrate, and electrically coupled to the first side of the first substrate; at least one rivet having a first end arranged on and electrically coupled to the first side of the first substrate; and an encapsulant encapsulating the at least one power semiconductor die, the at least one rivet and the substrates. At least parts of a second side of the substrates are exposed from the encapsulant. A second end of the at least one rivet is exposed at the encapsulant and configured to accept a press fit pin such that the at least one power semiconductor die can be electrically contacted from the outside.

Abstract: One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.