Patents by Inventor Adrian Marinescu

Adrian Marinescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11555248
    Abstract: A method comprising: cold-spraying a surface of a substrate with a bond material to form a bond coating; and cold-spraying a surface of the bond coating with a coating material to form a top coating. The bond material is different from the coating material and harder than the surface of the substrate.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: January 17, 2023
    Assignee: Rolls-Royce PLC
    Inventors: Feng Li, Iulian Marinescu, Adrian W Y Tan, Sun Wen, Erjia Liu
  • Patent number: 11391019
    Abstract: A system for routing fluid in a fluid system of a machine includes one or more hoses and one or more clamping arrangements. The hoses are adapted to extend from a main control valve, pass through a frame portion of the machine, and reach up to an end of a fluid cylinder to route fluid between the main control valve and the fluid cylinder and actuate the fluid cylinder. An actuation of the fluid cylinder powers a movement of an implement of the machine. The clamping arrangements are adapted to secure corresponding portions of the one or more hoses to corresponding locations on the frame portion of the machine. One clamping arrangement is interchangeable with another clamping arrangement to secure a corresponding portion of any hose of the one or more hoses to a corresponding location on the frame portion of the machine.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: July 19, 2022
    Assignee: Caterpillar Inc.
    Inventors: Dragos Marinescu, Srinivas Venkata Vasa, Adrian Stefan Spanoche
  • Patent number: 11301142
    Abstract: The current document is directed to an efficient and non-blocking mechanism for flow control within a multi-processor or multi-core processor with hierarchical memory caches. Traditionally, a centralized shared-computational-resource access pool, accessed using a locking operation, is used to control access to a shared computational resource within a multi-processor system or multi-core processor. The efficient and non-blocking mechanism for flow control, to which the current document is directed, distributes local shared-computational-resource access pools to each core of a multi-core processor and/or to each processor of a multi-processor system, avoiding significant computational overheads associated with cache-controller contention-control for a traditional, centralized access pool and associated with use of locking operations for access to the access pool.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 12, 2022
    Assignee: VMware, Inc.
    Inventor: Adrian Marinescu
  • Patent number: 11144227
    Abstract: Techniques for implementing content-based post-process data deduplication are provided. In one set of embodiments, a computer system can receive a write request comprising write data to be persisted to a storage system and can sample a portion of the write data. The computer system can further execute one or more analyses on the sampled portion in order to determine whether the write data is a good deduplication candidate that is likely to contain redundancies which can be eliminated via data deduplication. If the one or more analyses indicate that the write data is a good deduplication candidate, the computer system can cause the write data to be persisted to a staging storage component of the storage system. Otherwise, the computer system can cause the write data to be persisted to a primary storage component of the storage system that is separate from the staging storage component.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: October 12, 2021
    Assignee: VMWARE, INC.
    Inventors: Adrian Marinescu, Glen McCready
  • Patent number: 11086985
    Abstract: Examples described herein generally relate to a computer device including a memory, and at least one processor configured to determine whether to allow execution of an application file on the computer device. The processor receives a command to execute a file. The processor determines whether the file is associated with a package reputation of an installation package. The processor determines a file reputation of the file. The processor determines whether to allow execution of the file based on a combination of the file reputation of the file and whether the file is associated with the good package reputation.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 10, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Md. Nazmus Sakib, Thomas Walter Caldwell, III, Jeffrey Sutherland, Deskin Miller, Scott Anderson, Deepak Jagannathan Manohar, Adrian Marinescu
  • Publication number: 20190171809
    Abstract: Examples described herein generally relate to a computer device including a memory, and at least one processor configured to determine whether to allow execution of an application file on the computer device. The processor receives a command to execute a file. The processor determines whether the file is associated with a package reputation of an installation package. The processor determines a file reputation of the file. The processor determines whether to allow execution of the file based on a combination of the file reputation of the file and whether the file is associated with the good package reputation.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Md. Nazmus SAKIB, Thomas Walter CALDWELL, III, Jeffrey SUTHERLAND, Deskin MILLER, Scott ANDERSON, Deepak Jagannathan MANOHAR, Adrian MARINESCU
  • Publication number: 20190073151
    Abstract: Techniques for implementing content-based post-process data deduplication are provided. In one set of embodiments, a computer system can receive a write request comprising write data to be persisted to a storage system and can sample a portion of the write data. The computer system can further execute one or more analyses on the sampled portion in order to determine whether the write data is a good deduplication candidate that is likely to contain redundancies which can be eliminated via data deduplication. If the one or more analyses indicate that the write data is a good deduplication candidate, the computer system can cause the write data to be persisted to a staging storage component of the storage system. Otherwise, the computer system can cause the write data to be persisted to a primary storage component of the storage system that is separate from the staging storage component.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 7, 2019
    Inventors: Adrian Marinescu, Glen McCready
  • Patent number: 10152278
    Abstract: The present disclosure describes processing a write command directed to a block-based main storage device, and having a target logical sector and write data. The processing may include writing an address of a physical sector in the main storage device that contains the target logical sector to a header portion of a scratch block stored in a byte-addressable storage. The write data may be written to a slot the scratch block. The scratch block may be committed a scratch block in persistent storage. Subsequent to processing the write command, a write completion response may be signaled to the sender of the write command to indicate to the sender completion of the write command, without having committed the write data to the main storage device. Write data from several write commands may be subsequently committed to the main storage device.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 11, 2018
    Assignee: VMWARE, INC.
    Inventor: Adrian Marinescu
  • Patent number: 10108349
    Abstract: The current document is directed to a storage stack subsystem of a computer system that transfers data between memory and various data-storage devices and subsystems and that processes I/O requests. In one implementation, the disclosed storage stack includes a latency monitor, an I/O-scheduling bypass pathway, and short-circuit switch, controlled by the latency monitor. While the latency associated with I/O-request execution remains below a threshold latency, I/O-scheduling components of the storage stack are bypassed, with I/O requests routed directly to multiple input queues associated with one or more high-throughput multi-queue I/O device controllers. When the latency for execution of I/O requests rises above the threshold latency, I/O requests are instead directed to I/O-scheduling components of the storage stack, which attempt to optimally reorganize the incoming I/O-request stream and optimally distribute I/O-requests among multiple input queues associated I/O device controllers.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 23, 2018
    Assignee: VMware, Inc.
    Inventors: Adrian Marinescu, Thorbjoern Donbaek
  • Publication number: 20180275916
    Abstract: The present disclosure describes processing a write command directed to a block-based main storage device, and having a target logical sector and write data. The processing may include writing an address of a physical sector in the main storage device that contains the target logical sector to a header portion of a scratch block stored in a byte-addressable storage. The write data may be written to a slot the scratch block. The scratch block may be committed a scratch block in persistent storage. Subsequent to processing the write command, a write completion response may be signaled to the sender of the write command to indicate to the sender completion of the write command, without having committed the write data to the main storage device. Write data from several write commands may be subsequently committed to the main storage device.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 27, 2018
    Inventor: Adrian Marinescu
  • Publication number: 20170351441
    Abstract: The current document is directed to an efficient and non-blocking mechanism for flow control within a multi-processor or multi-core processor with hierarchical memory caches. Traditionally, a centralized shared-computational-resource access pool, accessed using a locking operation, is used to control access to a shared computational resource within a multi-processor system or multi-core processor. The efficient and non-blocking mechanism for flow control, to which the current document is directed, distributes local shared-computational-resource access pools to each core of a multi-core processor and/or to each processor of a multi-processor system, avoiding significant computational overheads associated with cache-controller contention-control for a traditional, centralized access pool and associated with use of locking operations for access to the access pool.
    Type: Application
    Filed: June 6, 2016
    Publication date: December 7, 2017
    Applicant: VMware, Inc.
    Inventor: Adrian Marinescu
  • Publication number: 20170351437
    Abstract: The current document is directed to a storage stack subsystem of a computer system that transfers data between memory and various data-storage devices and subsystems and that processes I/O requests at a greater rate than conventional storage stacks. In one implementation, the disclosed storage stack includes a latency monitor, an I/O-scheduling bypass pathway, and short-circuit switch, controlled by the latency monitor. While the latency associated with I/O-request execution remains below a threshold latency, I/O-scheduling components of the storage stack are bypassed, with I/O requests routed directly to multiple input queues associated with one or more high-throughput multi-queue I/O device controllers.
    Type: Application
    Filed: June 6, 2016
    Publication date: December 7, 2017
    Applicant: VMware, Inc.
    Inventors: Adrian Marinescu, Thorbjoern Donbaek
  • Patent number: 8844042
    Abstract: In some embodiments, a local agent on a target system may evaluate current and/or historical system state information from a store (either local or remote) and dynamically adjust the level of diagnosis performed during the scan based on the evaluated state information. Individual diagnostic scans may, for example, be enabled and disabled based on the context in the store, and each scan may update the context for further evaluation. By employing such an approach, systems with a low risk profile and lacking symptoms of a problem may be scanned quickly while systems that show signs of a problem or have a high risk profile may receive a more thorough evaluation.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: September 23, 2014
    Assignee: Microsoft Corporation
    Inventors: Randal P. Treit, Joseph J. Johnson, Adrian Marinescu, Nitin Sood, Marc E. Seinfeld
  • Publication number: 20130145350
    Abstract: A diagnostic system includes one or more processors for executing machine-executable instructions and one or more machine-readable storage media for storing the machine-executable instructions. The instructions include a plurality of traces. Each trace is a trace of events executing on a computing system. The system also includes processing logic configured to partition data in the trace into a first trace independent component which includes trace-independent information and a second trace dependent component which includes trace instance information. The system further includes a memory for storing the first trace independent component in a first data structure and the second trace dependent component in a second data structure.
    Type: Application
    Filed: December 5, 2011
    Publication date: June 6, 2013
    Applicant: MICROSOFT CORPORATION
    Inventor: Adrian Marinescu
  • Publication number: 20110314543
    Abstract: In some embodiments, a local agent on a target system may evaluate current and/or historical system state information from a store (either local or remote) and dynamically adjust the level of diagnosis performed during the scan based on the evaluated state information. Individual diagnostic scans may, for example, be enabled and disabled based on the context in the store, and each scan may update the context for further evaluation. By employing such an approach, systems with a low risk profile and lacking symptoms of a problem may be scanned quickly while systems that show signs of a problem or have a high risk profile may receive a more thorough evaluation.
    Type: Application
    Filed: June 16, 2010
    Publication date: December 22, 2011
    Applicant: Microsoft Corporation
    Inventors: Randal P. Treit, Joseph J. Johnson, Adrian Marinescu, Nitin Sood, Marc E. Seinfeld
  • Patent number: 7870558
    Abstract: Sharing access to resources using an inter-process communication (“IPC”) provides a connection in which references to resources are passed from a sender to a receiver in a trusted third party environment. A sender in possession of a reference to a resource, such as a handle to an object, may initiate the connection with the receiver. In turn, the receiver may accept or refuse the connection, and may further specify the types of resources in which the receiver is interested when accepting through the connection. Sharing access to resources in this manner advantageously insures that only a process that already has access to a resource is able to share that access with another process, and further that only processes that wish to do so will accept such access.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: January 11, 2011
    Assignee: Microsoft Corporation
    Inventors: Genevieve Fernandes, Adrian Marinescu, Neill M. Clift, Robert H. Earhart, Adnan Ilik
  • Patent number: 7802062
    Abstract: Buffer management system. A ring buffer may be implemented. The ring buffer includes a number of zones. Each of the zones includes state fields. The state fields include a filled indicator indicating whether the zone is full. The state fields for the zone further include a committed indicator indicating whether data in the zone is readable. The state fields for the zone also include a recycling indicator indicating whether the zone can be recycled. The ring buffer includes entries in the zones. Each of the entries includes state information. The entry state information includes a zone offset indication indicating a memory offset into the zone. The entry state information further includes a size indicating the size of the entry. The entry state information also includes a committed indicator indicating that the entry is readable.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: September 21, 2010
    Assignee: Microsoft Corporation
    Inventor: Adrian Marinescu
  • Patent number: 7784044
    Abstract: A system and method for automatically updating software components on a running computer system without requiring any interruption of service. A software module is hotpatched by loading a patch into memory and modifying an instruction in the original module to jump to the patch. A coldpatching technique places a coldpatch version of the module on disk for subsequent loading by processes, after hotpatching occurred. The coldpatch has the entry points to its functions at the same relative locations within the module as the hotpatch, which facilitates subsequent hotpatching. A hotpatch and coldpatch are automatically generated by deriving differences between changed and original binary files, and establishing the point to insert the jump. Validation is performed to ensure that the hotpatch is applied to the correct version, and that the coldpatch is replacing the correct version. Version management is also provided to control the number of patches via support rules.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: August 24, 2010
    Assignee: Microsoft Corporation
    Inventors: Garret J. Buban, Paul V. Donlan, Adrian Marinescu, Thomas D. McGuire, David B. Probert, Hoi H. Vo, Zheng Wang
  • Patent number: 7698741
    Abstract: Generally described, a method, software system, and computer-readable medium are provided for preventing a malware from colliding on a named object. In accordance with one aspect, a method is provided for creating a private namespace. More specifically, the method includes receiving a request to create a private namespace that contains data for defining the boundary of the private namespace from the current process. Then a determination is made regarding whether a principle associated with the current process has the security attributes that are alleged in the request. In this regard, if the principle that is associated with the current process has the security attributes that are alleged in the request, the method creates a container object to implement the private namespace that is defined by the data received in the request.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: April 13, 2010
    Assignee: Microsoft Corporation
    Inventors: Adrian Marinescu, Neill M Clift
  • Patent number: 7536428
    Abstract: A method and computing device for providing concurrent read and write access to a linked list of elements is presented. A linked list is provided wherein read access by a reader process and write access by a writer process may occur substantially concurrently. The linked list includes three internal lists for processes to reference elements of the linked list. The linked list also includes an updated indicator. Read access to the linked list is provided to a reader process such that the reader process accesses elements in the linked list according to a read list of the three internal lists. Write access to the linked list is provided to a writer process such that the writer process accesses elements in the linked list according to a write list of the three internal lists.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: May 19, 2009
    Assignee: Microsoft Corporation
    Inventors: Tahsin Erdogan, Adrian Marinescu, Dragos C. Sambotin