Patents by Inventor Adrian Marinescu
Adrian Marinescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11301142Abstract: The current document is directed to an efficient and non-blocking mechanism for flow control within a multi-processor or multi-core processor with hierarchical memory caches. Traditionally, a centralized shared-computational-resource access pool, accessed using a locking operation, is used to control access to a shared computational resource within a multi-processor system or multi-core processor. The efficient and non-blocking mechanism for flow control, to which the current document is directed, distributes local shared-computational-resource access pools to each core of a multi-core processor and/or to each processor of a multi-processor system, avoiding significant computational overheads associated with cache-controller contention-control for a traditional, centralized access pool and associated with use of locking operations for access to the access pool.Type: GrantFiled: June 6, 2016Date of Patent: April 12, 2022Assignee: VMware, Inc.Inventor: Adrian Marinescu
-
Patent number: 11144227Abstract: Techniques for implementing content-based post-process data deduplication are provided. In one set of embodiments, a computer system can receive a write request comprising write data to be persisted to a storage system and can sample a portion of the write data. The computer system can further execute one or more analyses on the sampled portion in order to determine whether the write data is a good deduplication candidate that is likely to contain redundancies which can be eliminated via data deduplication. If the one or more analyses indicate that the write data is a good deduplication candidate, the computer system can cause the write data to be persisted to a staging storage component of the storage system. Otherwise, the computer system can cause the write data to be persisted to a primary storage component of the storage system that is separate from the staging storage component.Type: GrantFiled: September 7, 2017Date of Patent: October 12, 2021Assignee: VMWARE, INC.Inventors: Adrian Marinescu, Glen McCready
-
Patent number: 11086985Abstract: Examples described herein generally relate to a computer device including a memory, and at least one processor configured to determine whether to allow execution of an application file on the computer device. The processor receives a command to execute a file. The processor determines whether the file is associated with a package reputation of an installation package. The processor determines a file reputation of the file. The processor determines whether to allow execution of the file based on a combination of the file reputation of the file and whether the file is associated with the good package reputation.Type: GrantFiled: December 4, 2017Date of Patent: August 10, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Md. Nazmus Sakib, Thomas Walter Caldwell, III, Jeffrey Sutherland, Deskin Miller, Scott Anderson, Deepak Jagannathan Manohar, Adrian Marinescu
-
Publication number: 20190171809Abstract: Examples described herein generally relate to a computer device including a memory, and at least one processor configured to determine whether to allow execution of an application file on the computer device. The processor receives a command to execute a file. The processor determines whether the file is associated with a package reputation of an installation package. The processor determines a file reputation of the file. The processor determines whether to allow execution of the file based on a combination of the file reputation of the file and whether the file is associated with the good package reputation.Type: ApplicationFiled: December 4, 2017Publication date: June 6, 2019Inventors: Md. Nazmus SAKIB, Thomas Walter CALDWELL, III, Jeffrey SUTHERLAND, Deskin MILLER, Scott ANDERSON, Deepak Jagannathan MANOHAR, Adrian MARINESCU
-
Publication number: 20190073151Abstract: Techniques for implementing content-based post-process data deduplication are provided. In one set of embodiments, a computer system can receive a write request comprising write data to be persisted to a storage system and can sample a portion of the write data. The computer system can further execute one or more analyses on the sampled portion in order to determine whether the write data is a good deduplication candidate that is likely to contain redundancies which can be eliminated via data deduplication. If the one or more analyses indicate that the write data is a good deduplication candidate, the computer system can cause the write data to be persisted to a staging storage component of the storage system. Otherwise, the computer system can cause the write data to be persisted to a primary storage component of the storage system that is separate from the staging storage component.Type: ApplicationFiled: September 7, 2017Publication date: March 7, 2019Inventors: Adrian Marinescu, Glen McCready
-
Patent number: 10152278Abstract: The present disclosure describes processing a write command directed to a block-based main storage device, and having a target logical sector and write data. The processing may include writing an address of a physical sector in the main storage device that contains the target logical sector to a header portion of a scratch block stored in a byte-addressable storage. The write data may be written to a slot the scratch block. The scratch block may be committed a scratch block in persistent storage. Subsequent to processing the write command, a write completion response may be signaled to the sender of the write command to indicate to the sender completion of the write command, without having committed the write data to the main storage device. Write data from several write commands may be subsequently committed to the main storage device.Type: GrantFiled: March 21, 2017Date of Patent: December 11, 2018Assignee: VMWARE, INC.Inventor: Adrian Marinescu
-
Patent number: 10108349Abstract: The current document is directed to a storage stack subsystem of a computer system that transfers data between memory and various data-storage devices and subsystems and that processes I/O requests. In one implementation, the disclosed storage stack includes a latency monitor, an I/O-scheduling bypass pathway, and short-circuit switch, controlled by the latency monitor. While the latency associated with I/O-request execution remains below a threshold latency, I/O-scheduling components of the storage stack are bypassed, with I/O requests routed directly to multiple input queues associated with one or more high-throughput multi-queue I/O device controllers. When the latency for execution of I/O requests rises above the threshold latency, I/O requests are instead directed to I/O-scheduling components of the storage stack, which attempt to optimally reorganize the incoming I/O-request stream and optimally distribute I/O-requests among multiple input queues associated I/O device controllers.Type: GrantFiled: June 6, 2016Date of Patent: October 23, 2018Assignee: VMware, Inc.Inventors: Adrian Marinescu, Thorbjoern Donbaek
-
Publication number: 20180275916Abstract: The present disclosure describes processing a write command directed to a block-based main storage device, and having a target logical sector and write data. The processing may include writing an address of a physical sector in the main storage device that contains the target logical sector to a header portion of a scratch block stored in a byte-addressable storage. The write data may be written to a slot the scratch block. The scratch block may be committed a scratch block in persistent storage. Subsequent to processing the write command, a write completion response may be signaled to the sender of the write command to indicate to the sender completion of the write command, without having committed the write data to the main storage device. Write data from several write commands may be subsequently committed to the main storage device.Type: ApplicationFiled: March 21, 2017Publication date: September 27, 2018Inventor: Adrian Marinescu
-
Publication number: 20170351437Abstract: The current document is directed to a storage stack subsystem of a computer system that transfers data between memory and various data-storage devices and subsystems and that processes I/O requests at a greater rate than conventional storage stacks. In one implementation, the disclosed storage stack includes a latency monitor, an I/O-scheduling bypass pathway, and short-circuit switch, controlled by the latency monitor. While the latency associated with I/O-request execution remains below a threshold latency, I/O-scheduling components of the storage stack are bypassed, with I/O requests routed directly to multiple input queues associated with one or more high-throughput multi-queue I/O device controllers.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Applicant: VMware, Inc.Inventors: Adrian Marinescu, Thorbjoern Donbaek
-
Publication number: 20170351441Abstract: The current document is directed to an efficient and non-blocking mechanism for flow control within a multi-processor or multi-core processor with hierarchical memory caches. Traditionally, a centralized shared-computational-resource access pool, accessed using a locking operation, is used to control access to a shared computational resource within a multi-processor system or multi-core processor. The efficient and non-blocking mechanism for flow control, to which the current document is directed, distributes local shared-computational-resource access pools to each core of a multi-core processor and/or to each processor of a multi-processor system, avoiding significant computational overheads associated with cache-controller contention-control for a traditional, centralized access pool and associated with use of locking operations for access to the access pool.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Applicant: VMware, Inc.Inventor: Adrian Marinescu
-
Patent number: 8844042Abstract: In some embodiments, a local agent on a target system may evaluate current and/or historical system state information from a store (either local or remote) and dynamically adjust the level of diagnosis performed during the scan based on the evaluated state information. Individual diagnostic scans may, for example, be enabled and disabled based on the context in the store, and each scan may update the context for further evaluation. By employing such an approach, systems with a low risk profile and lacking symptoms of a problem may be scanned quickly while systems that show signs of a problem or have a high risk profile may receive a more thorough evaluation.Type: GrantFiled: June 16, 2010Date of Patent: September 23, 2014Assignee: Microsoft CorporationInventors: Randal P. Treit, Joseph J. Johnson, Adrian Marinescu, Nitin Sood, Marc E. Seinfeld
-
Publication number: 20130145350Abstract: A diagnostic system includes one or more processors for executing machine-executable instructions and one or more machine-readable storage media for storing the machine-executable instructions. The instructions include a plurality of traces. Each trace is a trace of events executing on a computing system. The system also includes processing logic configured to partition data in the trace into a first trace independent component which includes trace-independent information and a second trace dependent component which includes trace instance information. The system further includes a memory for storing the first trace independent component in a first data structure and the second trace dependent component in a second data structure.Type: ApplicationFiled: December 5, 2011Publication date: June 6, 2013Applicant: MICROSOFT CORPORATIONInventor: Adrian Marinescu
-
Publication number: 20110314543Abstract: In some embodiments, a local agent on a target system may evaluate current and/or historical system state information from a store (either local or remote) and dynamically adjust the level of diagnosis performed during the scan based on the evaluated state information. Individual diagnostic scans may, for example, be enabled and disabled based on the context in the store, and each scan may update the context for further evaluation. By employing such an approach, systems with a low risk profile and lacking symptoms of a problem may be scanned quickly while systems that show signs of a problem or have a high risk profile may receive a more thorough evaluation.Type: ApplicationFiled: June 16, 2010Publication date: December 22, 2011Applicant: Microsoft CorporationInventors: Randal P. Treit, Joseph J. Johnson, Adrian Marinescu, Nitin Sood, Marc E. Seinfeld
-
Patent number: 7870558Abstract: Sharing access to resources using an inter-process communication (“IPC”) provides a connection in which references to resources are passed from a sender to a receiver in a trusted third party environment. A sender in possession of a reference to a resource, such as a handle to an object, may initiate the connection with the receiver. In turn, the receiver may accept or refuse the connection, and may further specify the types of resources in which the receiver is interested when accepting through the connection. Sharing access to resources in this manner advantageously insures that only a process that already has access to a resource is able to share that access with another process, and further that only processes that wish to do so will accept such access.Type: GrantFiled: July 15, 2005Date of Patent: January 11, 2011Assignee: Microsoft CorporationInventors: Genevieve Fernandes, Adrian Marinescu, Neill M. Clift, Robert H. Earhart, Adnan Ilik
-
Patent number: 7802062Abstract: Buffer management system. A ring buffer may be implemented. The ring buffer includes a number of zones. Each of the zones includes state fields. The state fields include a filled indicator indicating whether the zone is full. The state fields for the zone further include a committed indicator indicating whether data in the zone is readable. The state fields for the zone also include a recycling indicator indicating whether the zone can be recycled. The ring buffer includes entries in the zones. Each of the entries includes state information. The entry state information includes a zone offset indication indicating a memory offset into the zone. The entry state information further includes a size indicating the size of the entry. The entry state information also includes a committed indicator indicating that the entry is readable.Type: GrantFiled: September 28, 2007Date of Patent: September 21, 2010Assignee: Microsoft CorporationInventor: Adrian Marinescu
-
Patent number: 7784044Abstract: A system and method for automatically updating software components on a running computer system without requiring any interruption of service. A software module is hotpatched by loading a patch into memory and modifying an instruction in the original module to jump to the patch. A coldpatching technique places a coldpatch version of the module on disk for subsequent loading by processes, after hotpatching occurred. The coldpatch has the entry points to its functions at the same relative locations within the module as the hotpatch, which facilitates subsequent hotpatching. A hotpatch and coldpatch are automatically generated by deriving differences between changed and original binary files, and establishing the point to insert the jump. Validation is performed to ensure that the hotpatch is applied to the correct version, and that the coldpatch is replacing the correct version. Version management is also provided to control the number of patches via support rules.Type: GrantFiled: December 2, 2002Date of Patent: August 24, 2010Assignee: Microsoft CorporationInventors: Garret J. Buban, Paul V. Donlan, Adrian Marinescu, Thomas D. McGuire, David B. Probert, Hoi H. Vo, Zheng Wang
-
Patent number: 7698741Abstract: Generally described, a method, software system, and computer-readable medium are provided for preventing a malware from colliding on a named object. In accordance with one aspect, a method is provided for creating a private namespace. More specifically, the method includes receiving a request to create a private namespace that contains data for defining the boundary of the private namespace from the current process. Then a determination is made regarding whether a principle associated with the current process has the security attributes that are alleged in the request. In this regard, if the principle that is associated with the current process has the security attributes that are alleged in the request, the method creates a container object to implement the private namespace that is defined by the data received in the request.Type: GrantFiled: December 6, 2005Date of Patent: April 13, 2010Assignee: Microsoft CorporationInventors: Adrian Marinescu, Neill M Clift
-
Patent number: 7536428Abstract: A method and computing device for providing concurrent read and write access to a linked list of elements is presented. A linked list is provided wherein read access by a reader process and write access by a writer process may occur substantially concurrently. The linked list includes three internal lists for processes to reference elements of the linked list. The linked list also includes an updated indicator. Read access to the linked list is provided to a reader process such that the reader process accesses elements in the linked list according to a read list of the three internal lists. Write access to the linked list is provided to a writer process such that the writer process accesses elements in the linked list according to a write list of the three internal lists.Type: GrantFiled: October 23, 2006Date of Patent: May 19, 2009Assignee: Microsoft CorporationInventors: Tahsin Erdogan, Adrian Marinescu, Dragos C. Sambotin
-
Publication number: 20090089495Abstract: Buffer management system. A ring buffer may be implemented. The ring buffer includes a number of zones. Each of the zones includes state fields. The state fields include a filled indicator indicating whether the zone is full. The state fields for the zone further include a committed indicator indicating whether data in the zone is readable. The state fields for the zone also include a recycling indicator indicating whether the zone can be recycled. The ring buffer includes entries in the zones. Each of the entries includes state information. The entry state information includes a zone offset indication indicating a memory offset into the zone. The entry state information further includes a size indicating the size of the entry.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: MICROSOFT CORPORATIONInventor: Adrian Marinescu
-
Patent number: 7467158Abstract: Object virtualization provides a hierarchy of layers of spaces in which an object is accessible. The hierarchy of layers may include a physical layer containing the physical space in which the object is accessible, and virtual layers containing an arbitrary number of virtual spaces in which an object is accessible. Each virtual space is isolated from one another, so that objects accessible in one virtual space may not necessarily be accessible in another. Interfaces to objects that may be accessible in spaces in the hierarchy of layers facilitate accessing objects in the appropriate space. The appropriate space may be determined from the order of the layers in the hierarchy, alone or in combination with other information about the object and/or the component accessing the object. Accessing the objects in the appropriate space advantageously reduces or eliminates the number of namespace collisions in a computer system.Type: GrantFiled: June 10, 2005Date of Patent: December 16, 2008Assignee: Microsoft CorporationInventor: Adrian Marinescu