Abstract: A receiver (1300) includes a mixing digital-to-analog converter (DAC) (1306), a direct digital frequency synthesizer (DDFS) (132A) and an interface (134D). The mixing DAC (1306) includes a radio frequency (RF) transconductance section (1308) and a switching section (1310). The RE transconductance section (1308) includes an input for receiving an RF signal and an output for providing an RE current signal. The switching section (1310) is coupled to the RF transconductance section (1308) and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (132A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (1310). The interface (134D) is coupled to the DDFS (132A) and is configured to align the bits provided by the DDFS (132A) with a first clock signal.

Abstract: A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

Abstract: A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output. The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input.

Abstract: A receiver (100) includes a mixing digital-to-analog converter (DAC) (120), a direct digital frequency synthesizer (DDFS) (116), and a clock circuit (114). The mixing DAC (120) includes a radio frequency (RF) transconductance section (124) and a switching section (128). The RF transconductance section (124) includes an input configured to receive an RF signal. The switching section is coupled to the RF transconductance section (124) and includes inputs, configured to receive bits associated with a digital local oscillator (LO) signal, and an output. The DDFS (116) includes outputs, configured to provide the bits associated with the digital LO signal to the inputs of the switching section (128), and a first clock input, configured to receive a first clock signal that sets a sample rate for the digital LO signal The clock circuit (114) is configured to provide the first clock signal to the first clock input of the DDFS (116) at a frequency that is based on a selected channel.

Abstract: A technique includes receiving a signal spectrum that includes a plurality of channels within a first frequency range. The technique includes receiving a selection signal that identifies at least one desired channel to be tuned. The technique includes providing an oscillator that has a second frequency range that is substantially the same as the first frequency range and controlling the oscillators to generate one of a plurality of coarse-tune analog mixing signals. The signals substantially span across the second frequency range and each depends upon the location of the desired channel within the signal spectrum. The technique includes mixing the signal spectrum with the selected coarse-tune analog mixing signal to generate a coarsely tuned signal spectrum. The technique includes digitally processing the coarsely-tuned signal spectrum to fine tune the desired channel and to produce digital baseband signals for the desired channel.

Abstract: A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

Abstract: A receiver (1800) includes a mixing digital-to-analog converter (DAC) (1807), a direct digital frequency synthesizer (DDFS) (1848), a first power detector (1826), and a first control circuit (1834). The mixing DAC (1807) receives a digital local oscillator (LO) signal and a radio frequency (RF) signal and provides an output signal located in a first frequency band. The DDFS (1848) includes a first clock input that is configured to receive a first clock signal that sets a sample rate for the digital LO signal. The first power detector (1826) has an input coupled to an output of a switching section (1808) of the mixing DAC (1807). An output of the first power detector (1826) is configured to provide a channel power associated with the output signal.

Abstract: A receiver (100) includes a mixing digital-to-analog converter (DAC) (120), a direct digital frequency synthesizer (DDFS) (116), and a clock circuit (114). The mixing DAC (120) includes a radio frequency (RF) transconductance section (124) and a switching section. The RF transconductance section (124) includes an input configured to receive an RF signal. The switching section (128) is coupled to the RF transconductance section (124) and includes inputs configured to receive bits associated with a digital local oscillator (LO) signal. The DDFS (116) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (128) and a first clock input configured to receive a first clock signal that sets a sample rate for the digital LO signal. The clock circuit (114) is configured to provide the first clock signal to the first clock input of the DDFS (116).

Abstract: A receiver (100) includes a mixing digital-to-analog converter (DAC) (120), a direct digital frequency synthesizer (DDFS) (116), and a clock circuit (114). The mixing DAC (120) includes a radio frequency (RF) transconductance section (124) and a switching section (128). The RF transconductance section (124) includes an input configured to receive an RF signal. The switching section is coupled to the RF transconductance section (124) and includes inputs, configured to receive bits associated with a digital local oscillator (LO) signal, and an output. The DDFS (116) includes outputs, configured to provide the bits associated with the digital LO signal to the inputs of the switching section (128), and a first clock input, configured to receive a first clock signal that sets a sample rate for the digital LO signal The clock circuit (114) is configured to provide the first clock signal to the first clock input of the DDFS (116) at a frequency that is based on a selected channel.

Abstract: A receiver (400) includes a mixing digital-to-analog converter (DAC) (410), a direct digital frequency synthesizer (DDFS) (402), a scrambler (404), a decoder (406), and a multiplexer (408). The DDFS (402) includes outputs configured to provide bits associated with a digital local oscillator (LO) signal to control inputs of the mixing DAC (410). The scrambler (404) includes inputs coupled to the outputs of the DDFS (402) and is configured to scramble the bits of the digital LO signal. The decoder (406) includes inputs coupled to the outputs of the DDFS (402). The decoder (406) is configured to provide the bits of the digital LO signal without scrambling. The multiplexer (408) includes first inputs coupled to outputs of the scrambler (404), second inputs coupled to outputs of the decoder (406), and outputs coupled to the control inputs of the DDFS (402).

Abstract: A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input.

Abstract: A receiver (200) includes a mixing digital-to-analog converter (DAC) (208), a direct digital frequency synthesizer (DDFS), a transimpedance amplifier (TIA) (204) and a first polyphase filter (PPF) (202). The mixing DAC (208) includes a radio frequency (RF) transconductance section for providing an RF current signal responsive to an RF signal and a switching section. The switching section is coupled to the RF transconductance section and includes inputs for receiving bits associated with a digital local oscillator (LO) signal. The switching section is configured to mix the RF current signal with the digital LO signal to provide an analog output signal at outputs of the switching section. The transimpedance amplifier (TIA) (204) includes inputs each coupled to a respective one of the outputs of the switching section and outputs. The first PPF (202) includes inputs each coupled to a respective one the outputs of the TIA (204).

Abstract: A receiver (1300) includes a mixing digital-to-analog converter (DAC) (1306), a direct digital frequency synthesizer (DDFS) (132A) and an interface (134D). The mixing DAC (1306) includes a radio frequency (RF) transconductance section (1308) and a switching section (1310). The RE transconductance section (1308) includes an input for receiving an RF signal and an output for providing an RE current signal The switching section (1310) is coupled to the RF transconductance section (1308) and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (132A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (1310).

Abstract: A receiver (300) includes a mixing digital-to-analog converter (DAC) (118A), a direct digital frequency synthesizer (DDFS) (132) and a dynamic element matching (DEM) circuit (304). A DAC of the mixing DAC (118A) is implemented as a segmented DAC having a thermometer encoded DAC section (120A) and a binary encoded DAC section (120B). The DDFS (132) includes outputs configured to provide bits associated with a digital LO signal to inputs of a switching section (124A, 124B) of the mixing DAC (118A). The DEM circuit (304) is coupled between the outputs of the DDFS (132) and the inputs of the switching section (124A) that are associated with the thermometer encoded DAC section (120A). The DEM circuit (304) is configured to scramble the bits provided to the thermometer encoded DAC section (120A).

Abstract: A receiver (300) includes a mixing digital-to-analog converter (DAC) (118A), a direct digital frequency synthesizer (DDFS) (132) and a dynamic element matching (DEM) circuit (304). A DAC of the mixing DAC (118A) is implemented as a segmented DAC having a thermometer encoded DAC section (120A) and a binary encoded DAC section (120B). The DDFS (132) includes outputs configured to provide bits associated with a digital LO signal to inputs of a switching section (124A: 124B) of the mixing DAC (118A). The DEM circuit (304) is coupled between the outputs of the DDFS (132) and the inputs of the switching section (124A) that are associated with the thermometer encoded DAC section (120A). The DEM circuit (304) is configured to scramble the bits provided to the thermometer encoded DAC section (120A).

Abstract: A frequency synthesizer includes analog components and digital components. The frequency synthesizer includes at least one shunt regulator that is coupled to a supply rail to provide power to at least one of the digital components. The frequency synthesizer also includes at least one series regulator that is coupled to the supply rail to provide power to at least one of the analog components.

Abstract: A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

Abstract: High frequency laser diode (LD) and electro-absorption modulator (EAM) integrated circuit drivers using a cascaded output switch architecture that increases the output current and voltage edge speed and reduces the peaking and ringing of the output waveform, thus improving the deterministic jitter performance. Also disclosed is a method and apparatus that provides a modulation current dependence of both turn-on and turn-off driving currents that lead to an optimal compromise between the edge speed and output overshoot for a wide range of modulation currents. A PTAT temperature dependence of both voltage swing and current level in the predriver assures a low variation of the overshoot and rise/fall time over a wide temperature range. Using the cascaded output switch architecture provides an easy way of on-chip summation of the modulation and bias currents. Biasing the cascode device with a supply and modulation current dependent base voltage provides an optimum headroom output switch.

Abstract: Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path.

Abstract: Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path.