Abstract: A disclosed fuel cell system includes a fuel inlet that receives a fuel gas from a fuel source, a gas analyzer that determines a composition of the fuel gas received by the fuel inlet, and a stack including fuel cells that generate electricity using the fuel gas received from the fuel source. The fuel cell system further includes a controller that controls at least one of a fuel utilization of the stack, a current generated by the stack, or a voltage generated by the stack, based on the composition of the primary fuel gas determined by the gas analyzer. The controller may control the fuel cell system by increasing or decreasing a fuel flow rate to thereby increase or decrease the voltage generated by the stack to maintain a predetermined target voltage or to maintain a predetermined rate at which usable fuel is supplied to the stack based on composition.

Abstract: A ferroelectric memory array includes (a) a driver circuit providing a first signal and a second signal; (b) word lines each providing a word line signal; and (c) memory array sections. Each memory array section may include: (a) bit lines; (b) plate line segments each associated with a corresponding one of the word line signals; (c) local plate line decoders, each local plate line decoder (i) being associated with one of the plate line segments, (ii) receiving the corresponding word line signal of the associated plate line segment, the first signal and the second signal, and (iii) providing predetermined voltages on the associated plate line segment according to the received word line signal, the first signal and the second signal; and (d) memory cells, each memory cells having one or more ferroelectric capacitor connected between one of the plate line segments and one of the bit lines.

Abstract: A ferroelectric memory array includes (a) a driver circuit providing a first signal and a second signal; (b) word lines each providing a word line signal; and (c) memory array sections. Each memory array section may include: (a) bit lines; (b) plate line segments each associated with a corresponding one of the word line signals; (c) local plate line decoders, each local plate line decoder (i) being associated with one of the plate line segments, (ii) receiving the corresponding word line signal of the associated plate line segment, the first signal and the second signal, and (iii) providing predetermined voltages on the associated plate line segment according to the received word line signal, the first signal and the second signal; and (d) memory cells, each memory cells having one or more ferroelectric capacitor connected between one of the plate line segments and one of the bit lines.

Abstract: A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The processor may include a common address/data/control memory bus that is configured to provide an asynchronous handshaking interface between the memory array and the memory processor. The processor can offload error data from the memory chip for analysis, and can store poor retention bit address information for memory refreshing in a non-volatile error retention memory. Program logic can also be included for memory address re-configuration. Power management logic can also be included, which may have a process-voltage-temperature compensation voltage generator for providing stable and constant read currents. An asynchronous handshaking interface is provided between the memory array and the memory processor. Write error tagging and write verification circuits can also be included.

Abstract: A boost power converter system according to one embodiment includes an input voltage high-side node; an inductor coupled to the input voltage high-side node at a first terminal of the inductor; a power switch coupled to the inductor at a second terminal of the inductor; a drive circuit configured to control the power switch such that the boost power converter system operates in a discontinuous conduction mode when a load current drops below a critical conduction threshold; and a damping switch configured to enable current flow from the power switch at the second terminal of the inductor to the input voltage high-side node, wherein the damping switch is closed when the power switch is open and the damping switch is opened when the power switch is closed.

Abstract: Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

Abstract: A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The processor may include a common address/data/control memory bus that is configured to provide an asynchronous handshaking interface between the memory array and the memory processor. The processor can offload error data from the memory chip for analysis, and can store poor retention bit address information for memory refreshing in a non-volatile error retention memory. Program logic can also be included for memory address re-configuration. Power management logic can also be included, which may have a process-voltage-temperature compensation voltage generator for providing stable and constant read currents. An asynchronous handshaking interface is provided between the memory array and the memory processor. Write error tagging and write verification circuits can also be included.

Abstract: A boost power converter system according to one embodiment includes an input voltage high-side node; an inductor coupled to the input voltage high-side node at a first terminal of the inductor; a power switch coupled to the inductor at a second terminal of the inductor; a drive circuit configured to control the power switch such that the boost power converter system operates in a discontinuous conduction mode when a load current drops below a critical conduction threshold; and a damping switch configured to enable current flow from the power switch at the second terminal of the inductor to the input voltage high-side node, wherein the damping switch is closed when the power switch is open and the damping switch is opened when the power switch is closed.

Abstract: A configurable memory system and method is described wherein an integrated circuit coupled to a memory device includes application logic and memory interface logic in communication with the application logic, the memory interface logic configured to access a memory array within the memory device. The memory interface logic provides logic functions and/or signals that would have been provided by logic on a prior art memory device. The interface logic may access the memory device synchronously or asynchronously. The integrated circuit may communicate to the memory device using multiplexed or non-multiplexed signals.

Abstract: Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.

Abstract: A system is provided for testing a logic device and an integrated circuit disposed within a semiconductor device package. The logic device may be configured to operate in at least a normal mode and a test mode. A terminal external to the semiconductor device package may be electronically coupled to the logic device and the integrated circuit. The terminal may be configured to operate as a shared input for the logic device and the integrated circuit. A multiplexer circuit may be configured to convey a first signal from the terminal to the logic device in the test mode, to convey a second signal from the integrated circuit to the logic device in the normal mode, and to receive a third signal from the integrated circuit for causing a transition between the normal mode and the test mode.

Abstract: Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.

Abstract: Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within the underlying circuit. For example, the auxiliary circuit may be tested although it is mounted such that the interconnects are hidden, i.e., inaccessible for testing purposes after assembly using conventional testing systems and methods. The systems and methods further allow for including excess circuits and/or excess interconnects that can be reconfigured to replace parts of the auxiliary circuit and/or micro-scale interconnects found defective during testing.

Abstract: Disclosed are systems and methods of producing electronic devices. These electronic devices include excess circuits to be used as replacements for circuits that are found to be defective within the electronic device. The excess circuits are included in a different device component than the circuits that are found to be defective. The replacement process occurs after the excess circuits and defective circuits are included in an electronic device including the different device components. Identification of the defective circuits may occur before or after the defective circuits are incorporated in the electronic device. In some embodiments, systems and methods of the invention result in improved manufacturing yields as compared with the prior art.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test time sensitive parameters of the integrated circuit. The testing interface includes components for generating addresses, commands, and test data to be conveyed to the integrated circuit as well as a clock adjustment component. By adjusting the clock synchronization controlling the test signals to be conveyed to the integrated circuit, set-up time and hold time can be tested. The systems are configured to test set-up time and hold time of individual data channels, for example, an individual address line of the integrated circuit.

Abstract: A system is provided for testing a first integrated circuit associated with at least a second integrated circuit in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuits, and wherein the first integrated circuit is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit when the first integrated circuit is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit or an associated external terminal when the first integrated circuit is in test mode.

Abstract: A system is provided for testing a first integrated circuit chip associated with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit chip when the first integrated circuit chip is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit chip or an associated external terminal when the first integrated circuit chip is in test mode.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.