Abstract: Hardware may be created with different clock speeds used for different components of the system. Clock and throughput requirements on the interface circuitry of hardware components may set limits which are lower requirements for functional components. It may be advantageous to use more or fewer of some functional blocks or interface circuits in order to reduce cost, increase performance or reliability, reduce the requirements for additional parts, or other beneficial factors. Accordingly, it may be advantageous to generate hardware utilizing more than a single clock frequency. Generating instructions which indicate different clock frequencies for separate components may be difficult or time consuming; generating these instructions automatically may provide significant benefits in time savings, increased productivity, increased performance of hardware, or other benefits.

Abstract: Hardware may be created with different clock speeds used for different components of the system. Clock and throughput requirements on the interface circuitry of hardware components may set limits which are lower requirements for functional components. It may be advantageous to use more or fewer of some functional blocks or interface circuits in order to reduce cost, increase performance or reliability, reduce the requirements for additional parts, or other beneficial factors. Accordingly, it may be advantageous to generate hardware utilizing more than a single clock frequency. Generating instructions which indicate different clock frequencies for separate components may be difficult or time consuming; generating these instructions automatically may provide significant benefits in time savings, increased productivity, increased performance of hardware, or other benefits.