Abstract: A circuit and method to filter a signal is provided. The circuit includes a notch filter circuit to receive an input signal and first and second tuning signals and to provide an output signal. The notch filter circuit has an input-output frequency response that includes a stopband region. The stopband region has a center frequency and has an attenuation level that is based at least on a tuning signal. The tunable filter circuit further includes a tuning circuit operable in at least two modes to generate the tuning signal. The at least two modes includes a tuning mode and a filtering mode. The tuning circuit generates the tuning signal such that the attenuation level of the stopband region is greater in the filtering mode than in the tuning mode.

Abstract: A circuit and method to filter a signal is provided. The circuit includes a notch filter circuit to receive an input signal and first and second tuning signals and to provide an output signal. The notch filter circuit has an input-output frequency response that includes a stopband region. The stopband region has a center frequency and has an attenuation level that is based at least on a tuning signal. The tunable filter circuit further includes a tuning circuit operable in at least two modes to generate the tuning signal. The at least two modes includes a tuning mode and a filtering mode. The tuning circuit generates the tuning signal such that the attenuation level of the stopband region is greater in the filtering mode than in the tuning mode.

Abstract: A high gain amplifier includes a differential amplifier stage having a pair of transistors; first and second input circuits for providing input signals to the pair of transistors; transistor means arranged as a differential-to-single-ended converter driven by the differential amplifier stage to provide a single ended output signal; an intermediate gain stage having an input responsive to the single ended output signal; bias means for the differential amplifier, the bias means including circuit means for maintaining the currents through the pair of transistors in constant ratio independently of changes in load at the intermediate gain stage; and an inverting gain output stage driven by the intermediate gain stage and having an output for driving a load substantially from rail to rail. Also disclosed is a frequency compensation capacitor circuit connected between the input of the intermediate gain stage and the output of the inverting gain output stage.

Abstract: An integrated convective accelerometer device. The device includes a thermal acceleration sensor having a thermopile and a heater element; control circuitry for providing closed-loop control of the thermopile common-mode voltage; an instrumentation amplifier; clock generation circuitry; voltage reference circuitry; a temperature sensor; and, output amplifiers. The device can be operated in an absolute or ratiometric mode. Further, the device is formed in a silicon substrate using standard semiconductor processes and is packaged in a standard integrated circuit package.

Abstract: A current mirror replica biasing system where the resistor-programmable base current of a current reference transistor is accurately and scalably mirrored and input to the base of an output transistor, the current provided by the output transistor being useful as bias current to a load circuit, including a current reference transistor and an output transistor of like polarity; a pair of bipolar transistors, of like polarity to each other and opposite polarity to the current reference transistor and output transistor, arranged as a current mirror to mirror the base current of the current reference transistor, which base is exclusively interconnected to the input of the current mirror; and a current source to establish a desired reference current in the current reference transistor; wherein variations in the current source circuitry can result in circuit performance of the current mirror replica biasing system that is proportional to absolute temperature, or other desired function.

Abstract: A high gain amplifier includes a differential amplifier stage having a pair of transistors; first and second input circuits for providing input signals to the pair of transistors; transistor means arranged as a differential-to-single-ended converter driven by the differential amplifier stage to provide a single ended output signal; an intermediate gain stage having an input responsive to the single ended output signal; bias means for the differential amplifier, the bias means including circuit means for maintaining the currents through the pair of transistors in constant ratio independently of changes in load at the intermediate gain stage; and an inverting gain output stage driven by the intermediate gain stage and having an output for driving a load substantially from rail to rail. Also disclosed is a frequency compensation capacitor circuit connected between the input of the intermediate gain stage and the output of the inverting gain output stage.

Abstract: A high gain amplifier includes a differential amplifier stage having a pair of transistors; first and second input circuits for providing input signals to the pair of transistors; transistor means arranged as a differential-to-single-ended converter driven by the differential amplifier stage to provide a single ended output signal; an intermediate gain stage having an input responsive to the single ended output signal; bias means for the differential amplifier, the bias means including circuit means for maintaining the currents through the pair of transistors in constant ratio independently of changes in load at the intermediate gain stage; and an inverting gain output stage driven by the intermediate gain stage and having an output for driving a load substantially from rail to rail. Also disclosed is a frequency compensation capacitor circuit connected between the input of the intermediate gain stage and the output of the inverting gain output stage.

Abstract: A high gain amplifier includes an intermediate gain stage; an output gain stage driven by the intermediate gain stage; an input stage, for driving the intermediate gain stage, which is balanced between positive and negative feedback in normal operation; bias means for driving the input stage to maintain balance between positive and negative feedback in normal operation; and a resistance for limiting the output current of the intermediate stage in response to the input stage being overdriven into positive feedback.

Abstract: A dynamic bridge system with common mode range extension includes a dynamic bridge circuit having a pair of input terminals for receiving common mode and normal signals, a pair of intermediate terminals and an output terminal and reference terminal; a differential amplifier has its inputs connected to the intermediate terminals and its output connected to the output terminal; a pair of balanced loads is each connected at one end to an intermediate terminal; and an inverting amplifier responsive to the common mode signal at the inputs of the differential amplifier drives the other ends of the balanced loads in opposition to changes in the common mode signals at the inputs of the differential amplifier.

Abstract: A circuit for sensing a magnetic field has at least one saturable coil (L1). The circuit includes switches (S1, S2) controlled by a comparator (12) to drive the coil (L1) to saturation by alternating polarities of current. In the absence of an external magnetic field the currents are balanced. An applied external magnetic field causes an unbalance in the coil (L1) in reaching saturation. An unbalance current is applied through a sensing resistor (R2) to an integrator (20) to develop an output voltage (Vo) as a measure of the applied magnetic field. The switches (S1, S2) are implemented by transistor switches. Dual (FIG. 1) and single (FIG. 2) supply rail circuits are disclosed. The circuit finds particular application in torque transducers using magnetoelastic elements.

Abstract: A digital-to-analog converter of the type formed with a plurality of current source transistors arranged to carry different levels of current according to a predetermined weighting pattern, e.g., a binary weighting pattern. In the converter, a plurality of identically sized current source transistors carry the different levels of current and thus operate at different current densities with different base-to-emitter voltages subject to temperature drift. Stable emitter voltages, providing accurate levels of weighted current, are developed by means of resistances between the bases of successive current source transistors and a current source for developing across the interbase resistances a voltage linearly varying with absolute temperature, corresponding to the difference between base-to-emitter voltages of the successive current source transistors.

Abstract: A digital-to-analog converter of the type formed with a plurality of current source transistors arranged to carry different levels of current according to a predetermined weighting pattern, e.g., a binary weighting pattern. In the converter, a plurality of identically sized current source transistors carry the different levels of current and thus operate at different current densities with different base-to-emitter voltages subject to temperature drift. Stable emitter voltages, providing accurate levels of weighted current, are developed by means of resistances between the bases of successive current source transistors and a current source for developing across the interbase resistances a voltage linearly varying with absolute temperature, corresponding to the difference between base-to-emitter voltages of the successive current source transistors.