Abstract: A characterization device, system, and method for characterizing reflective elements from the light beams reflected in it. The device has two variable-gain detectors on a common structure, which can be portable or fixed, and for capturing light beams reflected by a reflective element, and from at least one processor characterizing the quality of the reflected light beams and evaluating the quality of the reflective element from its reflective capacity. Each detector has a lens for increasing the signal-to-noise ratio of the reflected beam or beams, a light sensor on which the beam or beams captured by the lens are focused, an automatic gain selection system associated with the optical sensor, and a data communication device associated with the device itself. A characterization system and a characterization method for characterizing reflective elements from the quality of the light beams reflected in at least one reflective element or heliostat.

Abstract: An integrated circuit includes a circuit area, and first and second scribe line portions. The first scribe line portion borders a first side of the circuit area, and the second scribe line portion borders a different second side of the circuit area. A plurality of dummy metal structures are located in the first and second scribe line portions, each of the dummy metal structures being located about at a lattice point of a same two-dimensional grid.

Abstract: In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.

Abstract: In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.

Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

Abstract: A cleaning system which can be integrated into a coater track system for use in the production of semiconductor devices and methods for its use are provided. The cleaning system can include a series of nozzles having assorted configurations and features which provide uniform and efficient rinsing of excess material.

Abstract: A cleaning system which can be integrated into a coater track system for use in the production of semiconductor devices and methods for its use are provided. The cleaning system can include a series of nozzles having assorted configurations and features which provide uniform and efficient rinsing of excess material.

Abstract: A method of forming a layer of photoresist 28 over a surface 30 of a semiconductor wafer 10 by forming a layer of pre-wet solvent 52 over the surface 30 and forming the layer of photoresist 28 over the layer of pre-wet solvent 52. Also, a layer of photoresist 28 formed by this method.

Abstract: A method of forming a layer of photoresist 28 over a surface 30 of a semiconductor wafer 10 by forming a layer of pre-wet solvent 52 over the surface 30 and forming the layer of photoresist 28 over the layer of pre-wet solvent 52. Also, a layer of photoresist 28 formed by this method.