Abstract: Biomarkers for prognosis of tumours, in hepatocellular carcinoma and other cancers. Measurement of biomarkers for prescription of anticancer immunotherapy targeted against ICOS+ regulatory T cells (TReg), e.g., selecting patients for treatment with an anti-ICOS antibody. Biomarkers comprising: (i) ratio of the number of ICOS FOXP3 double positive cells within a defined radius of influence around ICOS single positive cells to the total number of ICOS single positive cells, (ii) mean distance between each ICOS positive FOXP3 negative cell and its nearest ICOS FOXP3 double positive cell, (iii) proportion of FOXP3 positive cells which are ICOS positive, and (iv) density of ICOS positive cells.

Abstract: Various examples are directed to methods and system of managing a sensor. A measurement system may receive from the host device, a first register map describing a first configuration of the measurement system for the first sensor. The first configuration may indicate a first measurement frequency for the first sensor. The measurement system may configure a switch matrix to provide a first excitation signal to the first sensor. The measurement system may configure the switch matrix to connect an analog-to-digital converter (ADC) of the measurement system to the first sensor. The measurement system may sample a first raw sensor signal from the first sensor with the ADC at a first measurement frequency described by the first configuration. The measurement system may generate first digital measurement data based at least in part on the first raw sensor signal and send the first digital measurement data to the host device.

Abstract: Various examples are directed to systems and methods for managing a sensor. A measurement system may receive, from a host device, a first register map describing a first configuration of a measurement system. The first configuration may be associated with a first sensor. The measurement system may compare the first register map to an error rule set indicating inconsistent register map arrangements. After comparing the first register map to the error rule set, the measurement system may configure a switch matrix of the measurement system to sample the first sensor according to the first configuration of the measurement system. The measurement system may receive a plurality of samples from a first sensor and generate first digital measurement data based at least in part on the plurality of samples.

Abstract: A fault detection scheme can include use of a relatively high injection impedance between an input port for analog measurements from a sensor and a stimulus generation circuit controlled in coordination with analog measurement. The stimulus generation circuit can provide a stimulus signal through the injection impedance. A magnitude of the injection impedance can be specified relative to a source impedance associated with a source (e.g., a sensor or other device) coupled to the input port. For example, a magnitude of the injection impedance can be specified to be larger than the source impedance or the injection impedance magnitude can be specified to be a multiple of the source impedance.

Abstract: Various examples are directed to methods and system of managing a sensor. A measurement system may receive from the host device, a first register map describing a first configuration of the measurement system for the first sensor. The first configuration may indicate a first measurement frequency for the first sensor. The measurement system may configure a switch matrix to provide a first excitation signal to the first sensor. The measurement system may configure the switch matrix to connect an analog-to-digital converter (ADC) of the measurement system to the first sensor. The measurement system may sample a first raw sensor signal from the first sensor with the ADC at a first measurement frequency described by the first configuration. The measurement system may generate first digital measurement data based at least in part on the first raw sensor signal and send the first digital measurement data to the host device.

Abstract: Various examples are directed to systems and methods for managing a sensor. A measurement system may receive, from a host device, a first register map describing a first configuration of a measurement system. The first configuration may be associated with a first sensor. The measurement system may compare the first register map to an error rule set indicating inconsistent register map arrangements. After comparing the first register map to the error rule set, the measurement system may configure a switch matrix of the measurement system to sample the first sensor according to the first configuration of the measurement TO system. The measurement system may receive a plurality of samples from a first sensor and generate first digital measurement data based at least in part on the plurality of samples.

Abstract: Techniques to increase a data throughput rate of a filter circuit by preloading selectable memory circuits of the filter circuit with reference data, sampling input data at an input of the filter circuit, combining the sampled input data with the preloaded reference data, and generating a filter output based on the combined sampled input data and preloaded reference data.

Abstract: A fault detection scheme can include use of a relatively high injection impedance between an input port for analog measurements from a sensor and a stimulus generation circuit controlled in coordination with analog measurement. The stimulus generation circuit can provide a stimulus signal through the injection impedance. A magnitude of the injection impedance can be specified relative to a source impedance associated with a source (e.g., a sensor or other device) coupled to the input port. For example, a magnitude of the injection impedance can be specified to be larger than the source impedance or the injection impedance magnitude can be specified to be a multiple of the source impedance.

Abstract: A sigma-delta analog-to-digital converter (“?? ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ?? ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ?? ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.

Abstract: A sigma-delta analog-to-digital converter (“?? ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ?? ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ?? ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.

Abstract: Synchronous analog to digital conversion including providing a voltage analog to digital converter and a current analog to digital converter, synchronizing the converters, providing a signal conditioning circuit associated with the input of each converter, providing a current input to one of the signal conditioning currents and a voltage input to the other; and processing the inputs with gains differing by substantially an order of magnitude with substantially balanced time delays; and providing those conditioned inputs to the associated converters.

Abstract: A rapid response measurement is accomplished by providing to a programmable gain amplifier an input to be measured, providing to an analog to digital converter having a predetermined output rate, the output from the programmable gain amplifier, determining when the output is greater than full scale input range of the analog to digital converter in an interval shorter than the period of the predetermined output rate of the analog to digital converter and adjusting the gain of the programmable gain amplifier to reduce the output below the full scale of the analog to digital converter at a rate faster than the predetermined output rate of the ADC.

Abstract: A gain calibration system for an amplifier includes an amplifier having inputs and outputs and an analog to digital converter having inputs and an output. There is a voltage supply for providing a plurality of output voltages. A first switching circuit couples at least one of the output voltages to the inputs of the amplifier in a first phase. A second switching circuit couples the outputs of the amplifier to the inputs of the analog to digital converter in the first phase and couples the sum of all of the at least one output voltages to the input of the analog to digital converter in a second phase. A processor responsive to the outputs of the analog to digital converter in the first and second phases calculates a calibration factor to accommodate for amplifier gain error.

Abstract: A rapid response measurement is accomplished by providing to a programmable gain amplifier an input to be measured, providing to an analog to digital converter having a predetermined output rate, the output from the programmable gain amplifier, determining when the output is greater than full scale input range of the analog to digital converter in an interval shorter than the period of the predetermined output rate of the analog to digital converter and adjusting the gain of the programmable gain amplifier to reduce the output below the full scale of the analog to digital converter at a rate faster than the predetermined output rate of the ADC.

Abstract: Synchronous analog to digital conversion including providing a voltage analog to digital converter and a current analog to digital converter, synchronizing the converters, providing a signal conditioning circuit associated with the input of each converter, providing a current input to one of the signal conditioning currents and a voltage input to the other; and processing the inputs with gains differing by substantially an order of magnitude with substantially balanced time delays; and providing those conditioned inputs to the associated converters.

Abstract: A gain calibration system for an amplifier includes an amplifier having inputs and outputs and an analog to digital converter having inputs and an output. There is a voltage supply for providing a plurality of output voltages. A first switching circuit couples at least one of the output voltages to the inputs of the amplifier in a first phase. A second switching circuit couples the outputs of the amplifier to the inputs of the analog to digital converter in the first phase and couples the sum of all of the at least one output voltages to the input of the analog to digital converter in a second phase. A processor responsive to the outputs of the analog to digital converter in the first and second phases calculates a calibration factor to accommodate for amplifier gain error.

Abstract: A signal processing circuit comprising an ADC (5) to which differential signals and pseudo-differential signals are switched through two multiplexors (8) and (9). Positive input signals are buffered to a positive input terminal (6) of the ADC (5) through a buffer (12). Negative input signals are buffered through a conditioning circuit (15) to a negative input terminal (7) of the ADC (5). The conditioning circuit (15) comprises a buffer circuit (16) having a buffer (18), through which input signals are selectively buffered to the negative input terminal (7) of the ADC (5), and a bypass circuit (17) which bypasses the buffer circuit (18) for selectively passing input signals unbuffered to the negative input terminal (7) of the ADC 5.

Abstract: A circuit used for testing an integrated circuit including a chop circuit. A source of a test signal coupled to a first pair of pins of the integrated circuit. A test signal measuring device to measure the test signal coupled to a second pair of pins of the integrated circuit. A chop circuit controller produces a control signal and for feeding such control to the chop circuit and the test signal measuring device. In response to the control signal, the chop circuit couples the first pair of pins to the second pair of pins with a first polarity during a first period of time and couples the first pair of pins to the second pair of pins with an opposite polarity during a second period of time.

Abstract: An analog to digital conversion system having a plurality of analog to digital converters (ADCs). Each one of such ADCs is configured to convert a corresponding one of a plurality of analog signals into a corresponding sequence of digital words. The ADCs have different degrees of conversion performance. A source of the pulses is included. Each one of the ADCs is configured to provide a corresponding one of the sequences of digital words in response to the pulses. Each one of the digital words in each of the sequences is provided at substantially the same time. A controller is provided for interrupting and/or changing the configuration of one or more of the ADCs. The controller provides the interrupt and/or change in configuration with a priority to one of the ADCs over the other one of the ADCs.

Abstract: A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.