Abstract: A sleeve worn on an arm allows detection of gestures by an array of sensors. Electromyography, inertial, and magnetic field sensors provide data that is processed to categorize gestures and translate the gestures into commands for robotic systems. Machine learning allows training of gestures to increase accuracy of detection for different users.

Abstract: Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.

Abstract: A sleeve worn on an arm allows detection of gestures by an array of sensors. Electromyography, inertial, and magnetic field sensors provide data that is processed to categorize gestures and translate the gestures into commands for robotic systems. Machine learning allows training of gestures to increase accuracy of detection for different users.

Abstract: Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.

Abstract: Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.

Abstract: Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.

Abstract: A method and apparatus to recognize, identify, and authenticate/verify humans and human behavior by using shadow characteristics data, as well as body data in the visible and invisible radiation spectrum.

Abstract: Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.

Abstract: Systems and methods for generating results of observations of signals acquired from by groups, including humans, animals, living matter in vitro and machines as members of a group. In some embodiments, the signals are EEG, EMG, EOG or other signals from a biologically active source. The signals are categorized by various criteria, and can be quantified. The categorized signals are combined to produce a result. The result can be displayed to a user, recorded, fed back to one or more signal sources, or used in further information processing.

Abstract: A method and apparatus to recognize, identify, and authenticate/verify humans and human behavior by using shadow characteristics data, as well as body data in the visible and invisible radiation spectrum.

Abstract: A methodology for describing an input-output behavior of a multi-level logic gate to process simultaneously a multiplicity of independent Boolean logic functions, with each Boolean function processing signals carried on an individual, separate channel. An embodiment may simultaneously process the same data with the same function or with different functions, multiple data with the same function, or multiple data with different functions. In addition, multi-level logic signals (having more than two levels) may be processed, so that a higher communication bandwidth may be obtained without necessarily increasing the number of traces (wires). Other embodiments are described and claimed.

Abstract: An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

Abstract: The system and method of the invention provide a method of compressing and decompressing an image by dividing the image into slices and utilizing memory manipulation to enhance the processing of the slices. The method utilizes the presence in an image of a certain gray level or color level remaining constant over a portion or portions of the image. Illustratively, when processing a two-dimensional image W*H, such an image may be divided into slices of dimension w*h. Each slice is represented in the form of a slice-value. In processing slices represented by a slice-value, the contents of the memory are searched for a match. The slice-value may then be encoded using the address in the memory, if a match is present in the memory. The content and organization of the memory may be changed and/or reorganized depending on whether a match is found and at what location in the memory the match is found. Illustratively, the memory may be a cache memory.

Abstract: Apparatus, methods, and computer program products are provided for generating a second set of equations requiring reduced numbers of computations from a first set of general equations, wherein each general equation defines coefficients in terms of a set of samples and a plurality of functions having respective values. A first set of tokens is initially assigned to the plurality of functions such that every value of the functions that has a different magnitude is assigned a different token, thereby permitting each general equation to be defined by the set of samples and their associated tokens. Each general equation is then evaluated and the samples having the same associated token are grouped together. A second set of tokens is then assigned to represent a plurality of unique combinations of the samples. The second set of equations is then generated based at least on the first and second sets of tokens.

Abstract: A method of evolving a circuit uses a heterogenous mix of models of both high and low levels of resolution.

Abstract: The present invention provides apparatus, methods, and computer program products for providing coefficients of a function representative of a signal. In one embodiment, the apparatus, methods, and computer program products of the present invention, taking advantage of the independence of samples, provide complete sets of coefficients of the function as each sample is received and corrects the updated coefficients for accuracy by applying a rotating reference system. As such, the apparatus, methods, and computer program products of the present invention are capable of providing accurate coefficients with decreased latency. In another, embodiment, the apparatus, methods, and computer program products of the present invention use learning models to derive complete sets of coefficients of functions as each sample is received.

Abstract: Apparatus, methods, and computer program products are provided for generating a second set of equations requiring reduced numbers of computations from a first set of general equations, wherein each general equation defines coefficients in terms of a set of samples and a plurality of functions having respective values. A first set of tokens is initially assigned to the plurality of functions such that every value of the functions that has a different magnitude is assigned a different token, thereby permitting each general equation to be defined by the set of samples and their associated tokens. Each general equation is then evaluated and the samples having the same associated token are grouped together. A second set of tokens is then assigned to represent a plurality of unique combinations of the samples. The second set of equations is then generated based at least on the first and second sets of tokens.

Abstract: Apparatus, methods, and computer program products are provided for generating a second set of equations requiring reduced numbers of computations from a first set of general equations, wherein each general equation defines coefficients in terms of a set of samples and a plurality of functions having respective values. A first set of tokens is initially assigned to the plurality of functions such that every value of the functions that has a different magnitude is assigned a different token, thereby permitting each general equation to be defined by the set of samples and their associated tokens. Each general equation is then evaluated and the samples having the same associated token are grouped together. A second set of tokens is then assigned to represent a plurality of unique combinations of the samples. The second set of equations is then generated based at least on the first and second sets of tokens.

Abstract: A system for efficient implementation of transforms. The implementation by flows of particles, and summation by a conservation low offers savings. In particular for an electronic implementation, a current mode implementation is described, by which replicators, sign changers are implemented by current mirrors and summation is performed in a node by Kirchoff″s law. The transform implementation is efficient for on-chip compression avoiding the need to convert to digital all signals from a sensing array. It is also an efficient implementation for direct control of an emitting array, such as a display which can be directly controlled with outputs from a transform block performing decompression.

Abstract: An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.