Abstract: Macroinstructions stored in a program memory MP of a data processor, read out succesively under the control of a program counter PC, are decoded in a control unit CN which establishes a macroroutine for the transfer and processing of data within the processor as well as between the latter and associated peripheral units. The control unit comprises a microinstruction memory MM addressed by a microinstruction counter CC which is supplied with a starting address from an address store MI at the beginning of any microroutine as determined by a decoding of the final microinstruction of the immediately preceding microroutine. The address store contains 16 groups of 8 cells each; a logic network RL.sub.1, responsive to various bit combinations from a primary decoder DC.sub.1 and a secondary decoder DC.sub.2 in an output circuit of microinstruction memory MM, selects one of the cells of a group activated by a multiplexer MT.sub.