Abstract: An integrated circuit package comprising an encapsulant, a semiconductor die in the encapsulant the semiconductor die comprising a plurality of die terminals, an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals and a land grid array provided on a bottom surface of the package. The land grid array comprises a plurality of package terminals, each package terminal configured to be soldered to a printed circuit board, and an opening, wherein the opening is aligned with the integrated waveguide launcher.

Abstract: A compact integrated circuit (IC) that outputs millimeter-wave energy can be assembled into a highly compact package that can utilize ultrasmall contacts and/or contacts arrange with nonstandard pitch. The millimeter-wave IC can be assembled onto an interposer that includes an integrated transition configured to be coupled to a millimeter-wave waveguide on a printed circuit board having contacts that have a standardized size and pitch.

Abstract: A circuit-board interposer includes contacts on a top surface and a bottom surface and includes a millimeter-wave coaxial transition structure formed using contacts on the top surface and vias extending into the interposer. A first via extends into the interposer to a first depth and is surrounded by additional vias that penetrate the interposer to a second depth smaller than the first depth. The interposer also includes a hollow conductive waveguide structure formed within the interposer that extends from the second depth to a third depth that has a first end and a second end. The first via extends into the waveguide at the first end and an aperture is present at the second end. The coaxial transition and the waveguide together are configured to couple millimeter-wave energy from a feed contact on the top surface of the interposer and direct it to the aperture.

Abstract: A system comprising: a waveguide assembly comprising a plurality of waveguides, the plurality of waveguides comprising at least a first waveguide and a second waveguide, and an integrated circuit package, IC package, comprising a plurality of launchers to one or more of transmit signalling to and receive signalling from a respective one of the plurality of waveguides, wherein the waveguide assembly comprises a surface configured to be coupled to the IC package and each of the plurality of waveguides comprises an opening in the surface configured to be aligned with its respective launcher, and wherein each of the openings has a major dimension and a minor dimension, wherein the major dimension is larger than the minor dimension, and wherein the major dimension of at least the opening of the first waveguide is oriented perpendicular to the major dimension of the opening of the second waveguide.

Abstract: An apparatus includes a printed circuit board (PCB), a solder pad, a signal via, a plurality of metalized vias, and a waveguide. The PCB has a first surface opposite a second surface and includes a first metal layer, a second metal layer having a waveguide opening, and a PCB channel region from the waveguide opening in the second metal layer to the second surface. The solder pad is positioned on the first surface of the PCB over the channel region, and the signal via is coupled to the solder pad and a via pad in the second metal layer within the waveguide opening. The plurality of metalized vias extend from the first surface to the second surface of the PCB and form a boundary around the channel region. The waveguide is affixed to the waveguide opening in the second metal layer.

Abstract: A method of manufacturing a device is provided. The method includes forming a first cavity in a first substrate with the first cavity having a first depth. A second cavity is formed in a second substrate with the second cavity having a second depth. The first cavity and the second cavity are aligned with each other. The first substrate is affixed to the second substrate to form a waveguide substrate having a hollow waveguide with a first dimension substantially equal to the first depth plus the second depth. A conductive layer is formed on the sidewalls of the hollow waveguide. The waveguide substrate is placed over a packaged semiconductor device, the hollow waveguide aligned with a launcher of the packaged semiconductor device.

Abstract: An integrated circuit package comprising an encapsulant, a semiconductor die in the encapsulant the semiconductor die comprising a plurality of die terminals, an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals and a land grid array provided on a bottom surface of the package. The land grid array comprises a plurality of package terminals, each package terminal configured to be soldered to a printed circuit board, and an opening, wherein the opening is aligned with the integrated waveguide launcher.

Abstract: A method of manufacturing a device is provided. The method includes forming a first cavity in a first substrate with the first cavity having a first depth. A second cavity is formed in a second substrate with the second cavity having a second depth. The first cavity and the second cavity are aligned with each other. The first substrate is affixed to the second substrate to form a waveguide substrate having a hollow waveguide with a first dimension substantially equal to the first depth plus the second depth. A conductive layer is formed on the sidewalls of the hollow waveguide. The waveguide substrate is placed over a packaged semiconductor device, the hollow waveguide aligned with a launcher of the packaged semiconductor device.

Abstract: A mechanism is provided to reduce a distance of a waveguide antenna from transmit and receive circuitry in an integrated circuit device die. This distance reduction is performed by providing vertical access to radio frequency connections on a top surface of the IC device die. A cavity in the encapsulant of the package can be formed to provide access to the connections and plated to perform a shielding function. A continuous connection from the RF pads is used as a vertical interconnect. The region around the vertical interconnect can be filled with encapsulant potting material and back grinded to form a surface of the semiconductor device package. A waveguide antenna feed can be plated or printed on the vertical interconnect on the surface of the package.

Abstract: A mechanism is provided to reduce a distance of a waveguide antenna from transmit and receive circuitry in an integrated circuit device die. This distance reduction is performed by providing vertical access to radio frequency connections on a top surface of the IC device die. A cavity in the encapsulant of the package can be formed to provide access to the connections and plated to perform a shielding function. A continuous connection from the RF pads is used as a vertical interconnect. The region around the vertical interconnect can be filled with encapsulant potting material and back grinded to form a surface of the semiconductor device package. A waveguide antenna feed can be plated or printed on the vertical interconnect on the surface of the package.

Abstract: One embodiment of a packaged semiconductor device includes: a redistributed layer (RDL) structure formed over an active side of a semiconductor die embedded in mold compound, the RDL structure includes a plurality of solder ball pads that in turn includes: a set of first solder ball pads located on a front side of the packaged semiconductor device within a footprint of the semiconductor die, and a set of second solder ball pads located on the front side of the packaged semiconductor device outside of the footprint of the semiconductor die, each first solder ball pad includes a first center portion having a first diameter measured between opposite outer edges of the first center portion, each second solder ball pad includes a second center portion having a second diameter measured between opposite outer edges of the second center portion, and the first diameter is smaller than the second diameter.

Abstract: A lead frame strip includes an array of lead frames. The lead frames each include a die pad and lead fingers that are spaced from the die pads and disposed along one or more sides of the die pads. The lead fingers have proximal ends near to the die pad and distal ends farther from the die pad. Connection bars extend between the lead frames. The lead fingers of adjacent lead frames extend from opposing sides of the connection bars. The connection bars have first portions where the lead fingers are connected thereto, and second portions between adjacent lead finger connections to the connection bar. The second portions are etched to form a bar that extends diagonally from a first one of the adjacent lead fingers connected thereto to a second one of the adjacent lead fingers connected thereto.

Abstract: The electronic device (100) of the invention comprises a semiconductor device (30) and a low-pass filter (20), which are present in a stacked configuration, and which together include a phase locked loop. The low-pass filter is preferably embodied by vertical trench capacitors, and preferably comprises a drift compensation part. The device (100) can be suitably provided in an open loop architecture. In a preferred embodiment, the low-pass filter comprises a large capacitor (C2) and a small capacitor (C1) connected in parallel, the large capacitor (C2) being connected in series with a resistor (R1).