Abstract: A method of scanning pixels, each pixel including a photodiode and a sense node formed in the substrate, including a transfer gate coupled between the photodiode and the sense node, and including a memory gate coupled between the photodiode and the transfer gate. The method switches a control signal, connected to a memory gate electrode of all pixels, alternately between a first voltage and a second voltage that is intermediate between the first voltage and a substrate voltage. The first voltage transfers all photo charge in each photodiode into the respective memory gate. The second voltage both (1) holds all photo charge already transferred into the memory gate and (2) blocks further transfer of photo charges into each memory gate. The method further includes reading out photo charge from the memory gate on a row-by-row basis while the control signal is at the second voltage.

Abstract: A method of scanning pixels, each pixel including a photodiode and a sense node formed in the substrate, including a transfer gate coupled between the photodiode and the sense node, and including a memory gate coupled between the photodiode and the transfer gate. The method switches a control signal, connected to a memory gate electrode of all pixels, alternately between a first voltage and a second voltage that is intermediate between the first voltage and a substrate voltage. The first voltage transfers all photo charge in each photodiode into the respective memory gate. The second voltage both (1) holds all photo charge already transferred into the memory gate and (2) blocks further transfer of photo charges into each memory gate. The method further includes reading out photo charge from the memory gate on a row-by-row basis while the control signal is at the second voltage.

Abstract: The invention relates to a semiconductor device with a semiconductor body comprising a CMOS image sensor with an active region having viewed in projection first sides and second sides perpendicular to the first sides said active region comprising a matrix of active pixels arranged in rows and columns, each pixel having a photosensitive region, the device further comprising a plurality of circuit elements for operating the pixel in the image forming process, the plurality of circuit elements comprising a first set of circuit elements for read-out of the columns and a second set of circuit elements for controlling the rows. According to the invention a first part of the plurality of circuit elements is positioned outside the matrix along one of the first sides and a second part of the plurality of circuit elements is positioned within the matrix of active pixels remote from the second sides.

Abstract: An array-based C-MOS sensor device is provided with a facility for on the basis of non-destructive cell readout generating a radiation dose-sensing signal. In particular, the facility is arranged for accessing a subset of multiple distributed C-MOS cells across the array and feeding by such accessed cells an algorithmic means for therein generating an overall feedback dose control signalization and/or an over-all trigger signalization.

Abstract: The invention relates to a semiconductor device with a semiconductor body comprising a CMOS image sensor with an active region having viewed in projection first sides and second sides perpendicular to the first sides said active region comprising a matrix of active pixels arranged in rows and columns, each pixel having a photosensitive region, the device further comprising a plurality of circuit elements for operating the pixel in the image forming process, the plurality of circuit elements comprising a first set of circuit elements for read-out of the columns and a second set of circuit elements for controlling the rows. According to the invention a first part of the plurality of circuit elements is positioned outside the matrix along one of the first sides and a second part of the plurality of circuit elements is positioned within the matrix of active pixels remote from the second sides.

Abstract: A method is described for operating a CMOS sensor array apparatus that has an electronic shutter mechanism with a collective transfer facility for transferring sensed pixel values to an output storage facility, a read facility for time-distributed reading of the transferred pixel values and preparing for a subsequent reset, and a reset facility for collectively resetting array pixels. In particular, the method operates both the transfer and reset facilities at staggered instants in an operating cycle on mutually exclusive subsets from the pixels.

Abstract: An array-based C-MOS sensor device is provided with a facility for on the basis of non-destructive cell readout generating a radiation dose-sensing signal. In particular, the facility is arranged for accessing a subset of multiple distributed C-MOS cells across the array and feeding by such accessed cells an algorithmic means for therein generating an overall feedback dose control signalization and/or an overall trigger signalization.

Abstract: The invention relates to a method of manufacturing an integrated circuit (404) on a die (402), wherein the die (402) forms a detachable part of a wafer (401) comprising a plurality of dies that are separated from each other by dicing lanes (403). The method comprises a step of applying a metallization pattern (407) in at least one of the dicing lanes (403) to form a communication bus comprising at least one communication bus circuit (405) that is part of the integrated circuit (404). Said step is followed by a step wherein the integrated circuit (404) is tested according to a predetermined testing method which uses the communication bus circuit (405) to communicate with the integrated circuit (404). This step is followed by a next step wherein the die (402) is detached from the wafer (401). The communication bus circuit (405) is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (404), it communicates in the wafer test mode.

Abstract: The invention relates to a method of manufacturing an integrated circuit (404) on a die (402), wherein the die (402) forms a detachable part of a wafer (401) comprising a plurality of dies that are separated from each other by dicing lanes (403). The method comprises a step of applying a metallization pattern (407) in at least one of the dicing lanes (403) to form a communication bus comprising at least one communication bus circuit (405) that is part of the integrated circuit (404). Said step is followed by a step wherein the integrated circuit (404) is tested according to a predetermined testing method which uses the communication bus circuit (405) to communicate with the integrated circuit (404). This step is followed by a next step wherein the die (402) is detached from the wafer (401). The communication bus circuit (405) is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (404), it communicates in the wafer test mode.