Abstract: An authorization machine may be used by an authorizing entity to aggregate and analyze multiple reports that are pertinent to a performer of entertainment. The authorization machine may determine the performer's potential earnings for performing at an event to occur in the future. This determination may be based on one or more revenue-related reports that describe past transactions attributable at least in part to the performer. The authorization machine may then determine a likelihood that the performer will actually attain the potential earnings by performing at the event. This likelihood may be determined as a risk score based on one or more sentiment-related reports that describe the performer's popularity. Based on the potential earnings and the likelihood of attaining them, the authorization machine may authorize an advance payment corresponding to the performer.

Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.

Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.

Abstract: A method of processing an input image for storage includes decomposing the input image into a number of images at various resolutions, subdividing at least some of these images into tiles (rectangular arrays) and storing a block (referred to as the "tile block") representing each of the tiles, along with an index that specifies the respective locations of the tile blocks. In specific embodiments, the tiles are 64.times.64 pixels or 128.times.128 pixels. The representations of the tiles are typically compressed versions of the tiles. In a specific embodiment, JPEG compression is used. In a specific embodiment, an operand image is recursively decomposed to produce a reduced image and a set of additional (or complementary) pixel data. At the first stage, the operand image is normally the input image, and, for each subsequent stage, the operand image is the reduced image from the previous stage.

Abstract: A method of processing an input image for storage includes decomposing the input image into a number of images at various resolutions, subdividing at least some of these images into tiles (rectangular arrays) and storing a block (referred to as the "tile block") representing each of the tiles, along with an index that specifies the respective locations of the tile blocks. In specific embodiments, the tiles are 64.times.64 pixels or 128.times.128 pixels. The representations of the tiles are typically compressed versions of the tiles. In a specific embodiment, JPEG compression is used. In a specific embodiment, an operand image is recursively decomposed to produce a reduced image and a set of additional (or complementary) pixel data. At the first stage, the operand image is normally the input image, and, for each subsequent stage, the operand image is the reduced image from the previous stage.

Abstract: An enhancement to a standard lossy image compression technique wherein a single set of side information is provided to allow decompression of the compressed file. Certain portions of the image are selected (either by the user or automatically) for more compression than other portions of the image. A particular embodiment is implemented for use with the JPEG image compression technique. JPEG calls for subdividing the image into blocks, transforming the array of pixel values in each block according to a discrete cosine transform (DCT) so as to generate a plurality of coefficients, quantizing the coefficients for each block, and entropy encoding the quantized coefficients for each block.

Abstract: A system for reducing image data redundancies through progressive sub-band coding. The image is separated into a selected plurality of sub-bands, and the sub-band with the largest non-redundant data content is chosen and used to predict the data in the other sub-bands. Only prediction error information of the predicted sub-bands encoded and transmitted together with the encoded chosen sub-band. An overall performance error signal can also be evaluated at the encoder's end and used to further improve performance. The sub-band encoding can be performed recursively to still further reduce the encoded data.

Abstract: A fast pipeline adder comprising a plurality of registered adder rows. In one embodiment, additions in the pipeline are realized in reclocked half adders. In another embodiment, modified adders are employed which accept two carry inputs and develop two carry outputs. The resulting number of individual cells is reduced to approximately half of those in the prior embodiment. In still another embodiment, switch means are included in each cell to delete the reclocking and in still another embodiment, the adders in the diagonal of the pipeline adder are provided with additional inputs to permit use of the pipeline adder in recursive addition applications. In still another embodiment, the cells are permitted to output the inverse of the intended signal, reducing thereby the physical realization of the cells and increasing the speed of the cells.

Abstract: An orthogonal transform processor comprising a rotator circuit, a look-up table and a communicator circuit. The rotator circuit performs the complex multiplications required of a rotator, the necessary coefficients are supplied by the look-up table, and the communicator circuit is charged with the task of accepting input signals, supplying the rotator with the signals necessary for each iteration, and delivering the resultant output signals. The rotator is realized with a matrix of spatially adjacent interconnected multiplier and adder modules, where each module comprises a portion of each of the multipliers necessary in the rotator.