Abstract: Provided herein are proteins capable of providing a mildew resistant phenotype, or mildew resistance, to plants belonging to the Kalanchoe genus. Also provided herein are nucleic acid sequences, or cDNA sequences, and genes encoding the present proteins. Further provided herein are methods using the proteins, nucleic acid sequences and genes for selecting mildew resistant Kalanchoe plants, such as Oidium kalanchoeae resistant Kalanchoe plants, and to generate mildew resistant Kalanchoe plants, such as Oidium kalanchoeae resistant Kalanchoe plants, comprising the present proteins, mRNA forms of the present cDNAs or the present genes.

Abstract: Provided herein are proteins capable of providing a mildew resistant phenotype, or mildew resistance, to plants belonging to the Kalanchoe genus. Also provided herein are nucleic acid sequences, or cDNA sequences, and genes encoding the present proteins. Further provided herein are methods using the proteins, nucleic acid sequences and genes for selecting mildew resistant Kalanchoe plants, such as Oidium kalanchoeae resistant Kalanchoe plants, and to generate mildew resistant Kalanchoe plants, such as Oidium kalanchoeae resistant Kalanchoe plants, comprising the present proteins, mRNA forms of the present cDNAs or the present genes.

Abstract: The present invention relates to proteins capable of providing a decorative flowering phenotype in plants and especially in plants belonging to the Kalanchoe genus. The present invention also relates to nucleic acid sequences, or cDNA sequences, and genes encoding the present proteins. The present invention further relates to use of the present proteins, nucleic acid sequences and genes for selecting decorative flowering Kalanchoe plants and decorative flowering Kalanchoe plants comprising the present proteins, mRNA forms of the present cDNAs or the present genes. Specifically, the present invention relates to proteins comprising an amino acid substitution of the amino acid histidine at position 136 and/or the amino acid alanine at position 338 of the methyl transferase protein of a Kalanchoe plant, wherein the amino acid substitution provides a decorative flowering phenotype in the present Kalanchoe plants.

Abstract: An electronic circuit is provided that comprises a plurality of storage elements (101-105) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.

Abstract: A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic circuit (14) of a next processing element (10a, 10, 10b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (10b) includes loading time points of loading all processing elements (10a, 10) other than the final processing element (10).

Abstract: Pipeline synchronisation device for transferring data between clocked devices having different clock frequencies. The Pipeline synchronisation device comprises a mousetrap buffer for exchanging data with one of said external devices said mousetrap buffer having a signalling output for coordinating the data exchange with the external device. The pipeline synchronisation device comprises further a synchroniser adapted to synchronising the change in a signalling output with the clock of the external device.

Abstract: An electronic circuit that comprises components that operate asynchronously of one another. An interface element has inputs coupled to a respective one of the components. The interface element supplies a logic output signal that is a logic function of signals at the inputs and dependent on the relative timing of the signals at the inputs. The electronic circuit is switched to a test mode, in which test input signals are applied to the electronic circuit from a test signal source. During test a difference is caused to occur between the time intervals after which the test signal source affects different ones of the signals at the inputs of the interface element. Preferably the test control circuit activates said difference in the test mode and not in the normal operating mode.

Abstract: A locally synchronous circuit module has a delay circuit having and input and output coupled to a clock input. The delay circuit provides a delay which when incorporated in a clock oscillator ensures a clock period that is at least as long as needed to transfer information between the storage elements. A handshake circuit is provided for generating handshake signals for timing information transfer between the locally synchronous circuit module and a further circuit. The handshake circuit comprises the delay circuit, so that at least part of the handshake signals during a handshake transaction are timed by travelling through the delay circuit and are applied to the clock input to clock the locally synchronous circuit module.

Abstract: An integrated circuit according to the invention comprises a plurality of units (C1, C2, C3, C4;1), having first inputs (2a, 2b, 2c) for receiving control signals (n,s,t) for setting an operational mode of the unit (1). The units (1) have a functional mode, a scan in mode, a scan out mode. In the functional mode (n=1,s=0,t=1) a logical operation is performed at signals (a,b) received at one or more second inputs (4a, 4b). The result of the logical operation is provided via an internal node (6) to an output (10). In the scan in mode (n=0,s=1,t=0) a value at a scan input is stored at the internal node (6). In the scan out mode (n=0,s=0,t=1) the value at the internal node (6) is provided to the output (10). The integrated circuit according to the invention further has an evaluate mode (n=1,s=0,t=0) in which the result of the logical operation at the input signals (a,b) is stored at the internal node (6), and in which the output (10) of the units is disabled.