Abstract: A semiconductor on insulator device has an insulator layer, an active layer (40) on the insulator layer, a lateral arrangement of collector (10), emitter (30) and base (20) on the active layer, and a high Base-dose region (70) extending under the emitter towards the insulator to suppress vertical current flowing under the emitter. This region (70) reduces the dependence of current-gain and other properties on the substrate (Handle-wafer) voltage. This region can be formed of the same doping type as the base, but having a stronger doping. It can be formed by masked alignment in the same step as an n type layer used as the body for a P-type DMOS transistor.

Abstract: A semiconductor on insulator device has an insulator layer, an active layer (40) on the insulator layer, a lateral arrangement of collector (10), emitter (30) and base (20) on the active layer, and a high Base-dose region (70) extending under the emitter towards the insulator to suppress vertical current flowing under the emitter. This region (70) reduces the dependence of current-gain and other properties on the substrate (Handle-wafer) voltage. This region can be formed of the same doping type as the base, but having a stronger doping. It can be formed by masked alignment in the same step as an n type layer used as the body for a P-type DMOS transistor.

Abstract: In important applications of circuits comprising transistors of the lateral DMOST type, such as (half) bridges, the voltage on the output may become higher or lower than the supply voltage or earth in the case of an inductive load. The injection of charge carriers into the substrate can be prevented by screening the drain (18) of the Low-Side transistor from the substrate by means of a p-type buried layer (13) and an n-type buried layer (14) below said p-type buried layer. In order to avoid parasitic npn-action between the n-type buried layer (14) and the n-type drain (18), not only the back-gate regions (16a, 16c) at the edge of the transistor, but also the back-gate regions (16b) in the center of the transistor, are connected to the p-type buried layer, for example by means of a p-type well. As a result, throughout the relatively high-ohmic buried layer, the potential is well defined, so that said npn-action is prevented.

Abstract: The invention relates to a half-bridge circuit comprising two series-connected n-channel DMOS transistors, in which the source of the one transistor, the low-side transistor T.sub.1, is connected to a low-voltage terminal V.sub.ss, and the drain of the other transistor, the high-side transistor T.sub.2, is connected to a high-voltage terminal V.sub.dd. The drain of the low-side transistor and the source of the high-side transistor are connected to the output terminal (4). The circuit is arranged in a semiconductor body having an n-type or p-type epitaxial layer (11) which is applied to a p-type substrate (10). In the epitaxial layer, two n-type regions are defined for the transistors, each of said regions forming a drift region of one of the transistors and being surrounded by a cup-shaped n-type zone in the semiconductor body. Within the n-type cup-shaped zone (12) of the low-side transistor T.sub.1, there is provided a p-type cup-shaped zone which isolates the drift region (15) of T.sub.

Abstract: The breakdown voltage at high current values can be reduced in a HV-MOST with a weakly doped drain extension and a conventional interdigitated source/drain configuration,so that the SOAR (safe operating area) is reduced. The invention is based inter alia on the recognition that breakdown occurs at the end faces of the drain fingers at high current values owing to current convergences and the accompanying Kirk effect. To widen the SOAR of the transistor, the tips 8 of the drain fingers 5, 6 are rendered inactive in that the source fingers 4 are locally interrupted. In an optimized embodiment, the source fingers 4 shorter than the drain fingers 5,6.

Abstract: An epitaxial layer with a doping of approximately 10.sup.12 atoms per cm.sup.2 is used in accordance with the resurf condition for the high-voltage circuit element in high-voltage integrated circuits of the resurf type. If the circuit comprises a zone which is provided in the epitaxial layer, which is of the same conductivity type as the substrate, and to which a high voltage is applied, the doping between this zone and the substrate must in addition be sufficiently high for preventing punch-through between the zone and the substrate. A known method of complying with these two requirements is to make the epitaxial layer very thick. It is found in practice, however, that this method is often not very well reproducible. According to the invention, the epitaxial layer is provided in the form of a high-ohmic layer which is doped from the upper side (3a) and from a buried layer (3b).

Abstract: It is possible for electrical breakdown to occur at a lower voltage in the case of a strong current in a lateral DMOST having a conventional interdigitated source/drain configuration as compared with lower current values. The invention is based on the recognition that this breakdown arises at the end faces of the drain fingers owing to current convergence at the ends of the fingers and the Kirk effect associated therewith. To increase the SOAR (safe operating area) of the transistor, the tips 11 of the drain fingers 7 are rendered inactive in that the source fingers 6 are locally interrupted. In an optimized embodiment, the source fingers are shorter than the drain fingers at the ends of these drain fingers.

Abstract: In many circuits in which a current is switched off, a high voltage appears at the drain electrode of a transistor, in particular in the case of an inductive load. When a lateral high-voltage DMOST is used, such a high voltage may lead to instability in the transistor characteristics or may even damage the transistor. To avoid this problem, the drain of a high-voltage LDMOST is locally provided with a strongly doped n-type zone 18, 21 (in the case of an n-channel transistor) which extends, seen from the surface, down into the semiconductor body to a greater depth than does the source zone 8, so that a pn-junction is formed at a comparatively great depth in the semiconductor body having a breakdown voltage that is lower than the BV.sub.ds of the transistor without this zone. The energy stored in the inductance may thus be drained off through breakdown of the pn-junction.

Abstract: An LIGBT includes an LDMOST structure in which the drain/anode 9, 13 is provided with a pn junction which injects charge carriers into the drift region 8. To prevent latch-up, the base region 6 of the LDMOST is provided with deep zones 6b of the same conductivity type as the base region which extend locally comparatively far into the drift region. These zones collect charge carriers injected by the anode into the drift region and form a low-ohmic connection to the source contact 11 for these charge carriers. Since these zones are provided locally only, the threshold voltage of the LDMOST is not or at least substantially not influenced by the deep zones. In a modification, a ballast series resistance is provided in the source zone, so that latch-up is counteracted also at high temperatures.

Abstract: A deep diffusion of the back-gate region provided in a self-aligned manner with respect to the gate electrode is necessary in a DMOS transistor for obtaining a sufficiently high punch-through voltage between source and drain. The combination of a comparatively heavy back-gate implantation and a light source implantation and a heavy source implantation with spacer on the gate electrode, and the use of interstitial diffusion and accelerated diffusion owing to crystal damage render it possible to carry out said diffusion of the back-gate region at a comparatively low temperature, for example below 950 .degree. C. This renders it possible to integrate a DMOST into, for example, standard VLSI CMOS where first .delta.V.sub.th and channel-profile implantations are carried out, and subsequently the poly gates are provided, which means that a diffusion step at a temperature above 1,000 .degree. C. of long duration is no longer allowed.

Abstract: A circuit arrangement for comparatively high powers, for example, for gas discharge lamps is protected against high currents, which may be caused inter alia by inrush effects or transients, by a semiconductor current limiter element V. The current limiter element comprises a semiconductor body of substantially a given conductivity type, for example the n-type. The main electrodes are provided at the upper and the lower surface of the semiconductor body and comprise two metal electrodes which are connected to the semiconductor body via highly doped contact zones. The doping of the interposed region is such that current saturation occurs from a certain voltage upon a rise in voltage between the main electrodes. In a first embodiment, buried floating p-type zones are formed in the interposed region, so that the element is a junction field effect transistor with floating gate.

Abstract: A semiconductor device of the RESURF type with a "low-side" lateral DMOST (LDMOST), comprising a semiconductor body (1) of predominantly a first conductivity type and a surface region (3) adjoining a surface (2) and of a second conductivity type. The LDMOST comprises a back gate region (5) of the first conductivity type provided in the surface region (3) with a source region (6) of the second conductivity type in the back gate region (5) and a channel region (7) defined between the source region (6) and an edge of the back gate region (5). A drain region (8) of the second conductivity type is present at a distance from the back gate region (5). A separation region (15) of the first conductivity type is provided around the LDMOST in the surface region (3), which separation region adjoins the surface (2) and extends towards the semiconductor body (1).

Abstract: A semiconductor device with a semiconductor body (1) includes a surface region (3) of a first conductivity type which adjoins a surface and in which a field effect transistor is provided which includes a channel region (7) with a gate electrode (8) above it, and a source region (4), a drain region (5) and a drain extension region (6). The drain extension region (6) serves to improve the drain breakdown voltage of the field effect transistor. In practice, a high breakdown voltage is accompanied by a comparatively high on-resistance of the transistor. According to the invention, the drain extension region (6) has a geometry different from that in known transistors, i.e.

Abstract: It is possible to limit the voltage across a diode to the level of the pinch-off voltage of a JFET in an integrated circuit by connecting the diode in series with the JFET. As a result, the voltage offered through the JFET can be higher than the breakdown voltage of the diode, which is of particular importance in high-voltage ICs in which a highly doped buried zone is formed below the diode for reducing leakage currents to the substrate. According to the invention, the JFET together with at least one further circuit element is formed in a common island surrounded by an island insulation region. The gate of the JFET extends along the edge of the island and is separated from the relevant portion of the island insulation region substantially only by the source of the JFET. In the pinch-off condition, the gate divides the island into a high-voltage portion and a low-voltage portion which is coupled to the diode.

Abstract: A semiconductor device of the RESURF type with a lateral DMOST (LDMOST), comprising a semiconductor body (1) of substantially a first conductivity type and a surface region (3) of a second conductivity type adjoining the surface (2). The LDMOST comprises a back gate region (5) of the first conductivity type provided in the surface region (3), with a source region (6) of the second conductivity type in the back gate region (5) and a channel region (7) defined between the source region (6) and an edge of the back gate region (5). A drain region (8) of the second conductivity type is at a distance from the back gate region (5). A number of breakdown voltage raising zones (9) of the first conductivity type are provided between the back gate region (5) and the drain region (8).

Abstract: It is usual in high-voltage integrated circuits to provide one or several breakdown-voltage-raising rings at the edge of a high-voltage island in the form of surface zones of the conductivity type opposite to that of the island. According to the invention, the function of these rings is locally taken over by one or several zones forming part of a circuit element and also provided with a breakdown-voltage-raising edge. Since the breakdown-voltage-raising zones are locally omitted alongside the island insulation, a major space saving can be achieved.

Abstract: A semiconductor device includes a substrate of a first conductivity type, a semiconductor layer of the second opposite conductivity type disposed thereon and a lateral high-voltage transistor provided therein and located above a buried layer of the second conductivity type. Between the base zone and the surface-adjoining collector contact zone is situated a FET having an gate electrode separated from the semiconductor layer by a barrier layer. The gate electrode is electrically connected to the emitter. As a result, with the use of the transistor in emitter follower arrangement in the situation in which the emitter is substantially at collector potential, the emitter-collector current is not pinched off.

Abstract: An integrated CMOS circuit having a transistor located in a p (or an n) well and a adjacent complementary transistor. The transistors are located in an epitaxial layer on a highly doped substrate. With use, for example, in bridge circuits having an inductive load, parasitic currents can occur, which give rise to "latch-up" and/or dissipation. This can be avoided by providing under the source zone of the transistor located beside the wells a second region having substantially the same doping and depth as the well, which is connected to the source zone.

Abstract: In full or half DC/AC bridge circuits, the current through the control circuit, by which the power transistors T1,T2 are switched, is derived from the high supply voltage via a resistor. In order to reduce this current and the dissipation associated therewith, the control circuit includes an additional switch, preferably a MOST T4, which is non-conducting when the inverter transistor T3 is conducting and which is conducting when the transistor T3 is non-conducting. The control circuit thus becomes practically currentless. When the control electrode is applied to a suitable voltage, the transistor T4 can be controlled by its source voltage and thus becomes self-controlling. Thus, the circuit can be kept simple. The bridge circuit is particularly suitable for use with gas discharge lamps.

Abstract: A semiconductor device has a surface zone which forms a planar pn junction with the surrounding substrate, this pn junction being biased in operation in the reverse direction. In order to increase the breakdown voltage, one or more floating zones are located beside the pn junction within the range of the depletion zone, which also form planar pn junctions with the substrate. According to the invention, the floating zones have an overall doping of at least 3.multidot.10.sup.11 and at most 5.multidot.10.sup.12 atoms/cm.sup.2, as a result of which they are substantially depleted at a high reverse voltage.