Abstract: A processor including computation groups, each computation group including computation cores, the processor being capable of simultaneously implementing a plurality of applications, each application being implemented by a computation core and possibly requiring a read-mode or write-mode access to an external memory connected to the processor. At least one core, called dedicated core, of at least one computation group is dedicated to management of the external memory, the management making it possible to temporally and spatially organize read-mode and write-mode accesses to the external memory of each application requiring a read or a write in the external memory implemented by the processor.

Abstract: Multiple-core processor to be connected, by way of communication ports, to a deterministic switched Ethernet network using virtual links to which items of equipment are connected, the processor including clusters each including cores, wherein at least one cluster of the processor implements a switch function that makes it possible to interconnect the items of equipment in the network. At least one cluster of the processor implements an end system function providing functions of sending and receiving data in the network, and at least one cluster of the processor implements an application.

Abstract: Multiple-core processor to be connected, by way of communication ports, to a deterministic switched Ethernet network using virtual links to which items of equipment are connected, the processor including clusters each including cores, wherein at least one cluster of the processor implements a switch function that makes it possible to interconnect the items of equipment in the network. At least one cluster of the processor implements an end system function providing functions of sending and receiving data in the network, and at least one cluster of the processor implements an application.

Abstract: A processor including computation groups, each computation group including computation cores, the processor being capable of simultaneously implementing a plurality of applications, each application being implemented by a computation core and possibly requiring a read-mode or write-mode access to an external memory connected to the processor. At least one core, called dedicated core, of at least one computation group is dedicated to management of the external memory, the management making it possible to temporally and spatially organize read-mode and write-mode accesses to the external memory of each application requiring a read or a write in the external memory implemented by the processor.

Abstract: Disclosed is a method and device for aiding ground navigation of an aircraft on an airport in which a current position and current heading of the aircraft are determined by a set of information sources. A first determination unit determines, according to the determined current position and current heading, and according to information obtained from an airport database, a current traffic lane on which the aircraft is situated, and parameters relating to a next intersection of the current traffic lane. Parameters relating to the next intersection include the position of the next intersection; and the distance between the next intersection and the current position of the aircraft. A head-up display unit overlays, on an environment in front of the aircraft, a first symbol illustrating the determined current traffic lane and a set of second symbols illustrating the determined parameters of the next intersection.

Abstract: The device (1) comprises means (4) for determining parameters relating to the next intersection of the current traffic lane and a head-up display system (7) for presenting symbols illustrating these parameters.