Patents by Inventor Adrien Ille

Adrien Ille has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Poly silicon based interface protection
    Patent number: 10411006
    Abstract: A semiconductor device includes an active device of a transistor disposed in a semiconductor substrate. An isolation layer is disposed at the semiconductor substrate, and a polysilicon substrate layer is disposed over the isolation layer and the semiconductor substrate. The polysilicon substrate layer includes a semiconductor device region of an interface protection circuit of the transistor.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gernot Langguth, Adrien Ille
  • Poly Silicon Based Interface Protection
    Publication number: 20170323882
    Abstract: A semiconductor device includes an active device of a transistor disposed in a semiconductor substrate. An isolation layer is disposed at the semiconductor substrate, and a polysilicon substrate layer is disposed over the isolation layer and the semiconductor substrate. The polysilicon substrate layer includes a semiconductor device region of an interface protection circuit of the transistor.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 9, 2017
    Inventors: Gernot Langguth, Adrien Ille
  • Semiconductor ESD circuit and method
    Patent number: 9478979
    Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 25, 2016
    Assignee: Infineon Technologies AG
    Inventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
  • Semiconductor ESD Circuit and Method
    Publication number: 20150229126
    Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
    Type: Application
    Filed: April 20, 2015
    Publication date: August 13, 2015
    Inventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
  • Semiconductor ESD circuit and method
    Patent number: 9013842
    Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
  • Semiconductor ESD Circuit and Method
    Publication number: 20120176710
    Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
    Type: Application
    Filed: January 10, 2011
    Publication date: July 12, 2012
    Inventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille