Abstract: Embodiments are described for a method for processing textures for a mesh comprising quadrilateral polygons for real-time rendering of an object or model in a graphics processing unit (GPU), comprising associating an independent texture map with each face of the mesh to produce a plurality of face textures, packing the plurality of face textures into a single texture atlas, wherein the atlas is divided into a plurality of blocks based on a resolution of the face textures, adding a border to the texture map for each face comprising additional texels including at least border texels from an adjacent face texture map, and performing linear interpolation of a trilinear filtering operation on the face textures to resolve resolution discrepancies caused when crossing an edge of a polygon.

Abstract: A method for validating standard cells stored in a standard cell library and for use in design of an integrated circuit device is described. Each standard cell of the standard cells is iteratively placed adjacent to each side and corner of itself and each other standard cell of the standard cells to produce an interim test layout comprising a first plurality of cell pair permutations. The cell pair permutations are reduced by identifying at least one of: illegal or redundant left-right and top-bottom boundaries, and removing any cell pair permutations using the identified boundaries to generate a final test layout comprising a second plurality of cell pair permutations.

Abstract: An apparatus and methods for hardware-based performance monitoring of a computer system are presented. The apparatus includes: processing units; a memory; a connector device connecting the processing units and the memory; probes inserted the processing units, and the probes generating probe signals when selected processing events are detected; and a thread trace device connected to the connector device. The thread trace device includes an event interface to receive probe signals, and an event memory controller to send probe event messages to the memory, where probe event messages are based on probe signals. The probe event messages transferred to memory can be subsequently analyzed using a software program to determine, for example, thread-to-thread interactions.

Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Abstract: A method, an apparatus, and a non-transitory computer readable medium for performing 2D to 3D conversion are presented. A 2D input source is extracted into left and right 3D images. Motion vectors are calculated for the left and right 3D images. Frame rate conversion is performed on the left 3D image and the right 3D image, using the respective calculated motion vectors, to produce motion compensated left and right 3D images. The left and right 3D images and the motion compensated left and right 3D images are reordered for display.

Abstract: A system and method are disclosed for recreating graphics processing unit (GPU) state information associated with a migrated virtual machine (VM). A VM running on a first VM host coupled to a first graphics device, comprising a first GPU, is migrated to a second VM host coupled to a second graphics device, in turn comprising a second GPU. A context module coupled to the first GPU reads its GPU state information in its native GPU state representation format and then converts the GPU state information into an intermediary GPU state representation format. The GPU state information is conveyed in the intermediary GPU state representation format to the second VM host, where it is received by a context module coupled to the second GPU. The context module converts the GPU state information related to the first GPU from the intermediary GPU state representation format to the native GPU state representation format of the second GPU.

Abstract: A system, method, and computer program product are provided for tessellation using shaders. New graphics pipeline stages implemented by shaders are introduced, including an inner ring shader, an outer edge shader, and topologic shader, which work together with a domain shader and geometry shader to provide tessellated points and primitives. A hull shader is modified to compute values used by the new shaders to perform tessellation algorithms. This approach provides parallelism and customizability to the presently static tessellation engine implementation.

Abstract: The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability.

Abstract: Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering.

Abstract: An embedded, programmable motion blur system and method is described. Embodiments include receiving a plurality of vertices in a graphics processing unit (GPU), displacing at least one vertex, receiving a primitive defined by at least one of the displaced vertices, and generating a plurality of primitive samples from the primitive. The receiving of a plurality of vertices, the displacing, the receiving a primitive, and the generating are all performed prior to rendering of the scene. The system includes a central processing unit (CPU), a memory unit coupled to the CPU, and at least one programmable GPU. The GPU includes a vertex shader and a geometry shader programmable to perform geometry amplification and generate a plurality of primitive samples, both of these performed before the scene is rendered.

Abstract: Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.

Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.

Abstract: A system and method for conducting a financial transaction is disclosed. The system includes a first memory location embedded in a personal portable device. The first memory location stores a plurality of personal financial data files associated with a user. The system also includes a second memory location to store biometric information and a first input interface to receive authentication information after initiation of a purchase transaction session. The system also includes a security module including an input coupled to the first interface to authenticate the authentication information based on the biometric information and an output interface comprising an input coupled to the first memory location and an output to provide personal financial data file information to a host device.

Abstract: A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Abstract: A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed.

Abstract: A system for decoding video data includes a processing unit. The processing unit includes a plurality of processing pipelines and a driver. The driver includes a decoder configured to generate a plurality of intermediate control maps containing control information including an indication of which macro blocks or portions of macro blocks may be processed in parallel in the plurality of processing pipelines.

Abstract: A filtering method and apparatus for anti-aliasing takes advantage of improved existing hardware by using as input the data stored in the multisampling anti-aliasing (MSAA) buffers after rendering. The standard hardware box-filter is then replaced with a more intelligent resolve implemented using shader programs. Embodiments find scene edges using existing samples generated by Graphics Processing Unit (GPU) hardware. Using samples from a footprint larger than a single pixel, a gradient is calculated matching the direction of an edge. A non-linear filter over contributing samples in the direction of the gradient gives the final result.

Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.