Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.

Abstract: A method for compressing an image includes decomposing the image into one or more regions. A region of the image is selected to be evaluated. The selected region is transformed and quantized if the region does not meet a predetermined compression acceptability criteria. The predetermined compression acceptability criteria may include a specific bit rate, a specific image quality, or combinations thereof. If the region does not meet the predetermined compression acceptability criteria after the region has been transformed and quantized, then the transformation and quantization settings are adjusted and the region is transformed and quantized using the adjusted settings. The region is then encoded when the predetermined compression acceptability criteria has been reached. The encoding may include additional compression stages.

Abstract: In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.

Abstract: An integrated circuit includes, in one example, an active memory cell array and a passive variable resistance memory cell array positioned above the active memory cell array, such as in upper layers of the integrated circuit. The active memory cell array and the passive variable resistance memory cell array share one or more components of memory control logic such as address decode logic, data read logic and/or data write logic. As such, a type of active memory and passive variable resistance memory hybrid structure shares memory control logic such as word line drivers, bit line drivers and read logic. The active memory cell array and passive variable resistance memory cell array overlap reducing integrated circuit die size, improving power reduction and reducing costs by sharing peripheral circuits.

Abstract: A method for switching decoding and rendering of a digital video stream from a first graphics processing unit (GPU) to a second GPU. The digital video stream is evaluated to determine an amount of time until a next intra-coded frame (I-frame) in the digital video stream. If the amount of time is below a threshold, decoding and rendering of the digital video stream is switched to the second GPU on the next I-frame in the digital video stream and decoding the digital video stream by the first GPU is stopped. If the amount of time is above the threshold, the digital video stream is decoded on both the first GPU and the second GPU, the rendering of the digital video stream is switched to the second GPU, and decoding the digital video stream by the first GPU is stopped.

Abstract: A method for forming an integrated circuit system includes providing an integrated circuit device; and forming an integrated contact over the integrated circuit device including: providing a via over the integrated circuit device; forming a selective metal in the via; forming at least one nanotube over the selective metal; and forming a cap over the nanotubes.

Abstract: A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.

Abstract: A method for performing channel estimation in an orthogonal frequency division multiplexing (OFDM) signal includes choosing reserved tones to be part of a pilot pattern, and using the reserved tones in the pilot pattern to perform the channel estimation. An apparatus for use in performing channel estimation in an OFDM system includes a receiver configured to receive a transmitted OFDM signal; a pilot symbol extractor configured to extract pilot symbols from the OFDM signal; and a channel estimator configured to perform the channel estimation, including using reserved tones as pilot tones.

Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

Abstract: A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) sends a garbage collection request and a first log to a special processing unit (SPU). The first log includes an address and a data size of each allocated data object stored in a heap in memory corresponding to the CPU. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU efficiently performs operations of a garbage collection algorithm due to its architecture on a local representation of the data objects stored in the memory. The SPU records a list of changes it performs to remove dead data objects and compact live data objects. This list is subsequently sent to the CPU, which performs the included operations.