Patents by Inventor ADVANCED SEMICONDUCTOR ENGINEERING,

ADVANCED SEMICONDUCTOR ENGINEERING, has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140252547
    Abstract: The present invention relates to a semiconductor device and a process for fabricating the same. In one embodiment, the semiconductor device includes a substrate and a plurality of integrated passive devices. The integrated passive devices are disposed on the substrate and include at least two capacitors which have different capacitance values.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: ADVANCED SEMICONDUCTOR ENGINEERING, Inc.
  • Publication number: 20140159098
    Abstract: The present invention relates to a semiconductor lead frame package and LED package. The semiconductor lead frame package includes a die pad, a lead, a die and an insulator body. The lead is electrically isolated from the die pad. The die is disposed on the die pad and electrically connected to the lead. The insulator body partially encapsulates the die pad and the lead, and has a top surface and a bottom surface, wherein a part of the lead is folded onto the top surface of the insulator body.
    Type: Application
    Filed: December 11, 2012
    Publication date: June 12, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
  • Publication number: 20130068517
    Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.
    Type: Application
    Filed: November 9, 2012
    Publication date: March 21, 2013
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: ADVANCED SEMICONDUCTOR ENGINEERING,