Patents by Inventor Adwait Telang

Adwait Telang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS AND APPARATUS TO PREVENT OVER-ETCH IN SEMICONDUCTOR PACKAGES
    Publication number: 20240222283
    Abstract: Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Hongxia Feng, Bohan Shan, Bai Nie, Xiaoxuan Sun, Holly Sawyer, Tarek Ibrahim, Adwait Telang, Dingying Xu, Leonel Arana, Xiaoying Guo, Ashay Dani, Sairam Agraharam, Haobo Chen, Srinivas Pietambaram, Gang Duan
  • Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias
    Patent number: 9716066
    Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: July 25, 2017
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, James Y. Jeong, Hsiao-Kang Chang, John Muirhead, Adwait Telang, Puneesh Puri, Jiho Kang, Nitin M. Patel
  • INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS
    Publication number: 20160049371
    Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
    Type: Application
    Filed: June 29, 2013
    Publication date: February 18, 2016
    Inventors: Kevin J. Lee, James Y. Jeong, Hsiao-Kang Chang, John Muirhead, Adwait Telang, Puneesh Puri, Jiho Kang, Nitin M. Patel
  • Tapered die-side bumps
    Publication number: 20080003715
    Abstract: Embodiments of the invention include apparatuses and methods relating to die-side bumps having a tapered cross-section. In one embodiment, the tapered die-side bump is electrically coupled to a solder bump on a package substrate.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Kevin J. Lee, Figen T. Akin, Kurt Schultz, Raman Vaidyanathan, Shane A. Nolen, Adwait Telang