Patents by Inventor Ady Tal

Ady Tal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
    Patent number: 9052947
    Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: June 9, 2015
    Assignee: Intel Corporation
    Inventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Welc
  • Unified Optimistic and Pessimistic Concurrency Control for a Software Transactional Memory (STM) System
    Publication number: 20140156953
    Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
    Type: Application
    Filed: September 16, 2013
    Publication date: June 5, 2014
    Inventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Welc
  • Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
    Patent number: 8555016
    Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Wele
  • UNIFIED OPTIMISTIC AND PESSIMISTIC CONCURRENCY CONTROL FOR A SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEM
    Publication number: 20100153953
    Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Inventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Wele
  • Optimizing binary-level instrumentation via instruction scheduling
    Publication number: 20070006167
    Abstract: In one embodiment, the present invention includes a method for receiving a command to insert instrumentation code into a code segment, analyzing the code segment to determine an optimal location for the instrumentation code within the code segment, and inserting the instrumentation code at the optimal location to generate an instrumented code segment. The instrumented code segment may then be executed and may provide for improved performance over unoptimized instrumented code. Other embodiments are described and claimed.
    Type: Application
    Filed: May 31, 2005
    Publication date: January 4, 2007
    Inventors: Chi-Keung Luk, Ady Tal, Robert Cohn, Jonathan Beimel
  • Device, system and method of allocating spill cells in binary instrumentation using one free register
    Publication number: 20050071606
    Abstract: There are presented a method, device and system for allocating spill cells for an instrumentation fragment that is run on a processor that uses a register stack architecture where only one free register is available for such fragment.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Roman Talyansky, Vladimir Vladimirov, Dmitry Kaptsenel, Ady Tal, Amit Dagan