Patents by Inventor Ae-Hee CHOI

Ae-Hee CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10090266
    Abstract: A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip region. A center pad is provided on the chip region and on the integrated circuit, and a boundary pad is provided on the boundary region. The semiconductor device further includes a first lower insulating structure having a contact hole exposing the center pad, a second lower insulating structure, at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the first lower insulating structure, a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: October 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ae-Hee Choi, Sang-ki Kim, Ahyun Jo, Kyo-Seon Choi
  • Publication number: 20170062363
    Abstract: A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip region. A center pad is provided on the chip region and on the integrated circuit, and a boundary pad is provided on the boundary region. The semiconductor device further includes a first lower insulating structure having a contact hole exposing the center pad, a second lower insulating structure , at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the first lower insulating structure, a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip.
    Type: Application
    Filed: July 8, 2016
    Publication date: March 2, 2017
    Inventors: Ae-Hee CHOI, Sang-ki KIM, Ahyun JO, Kyo-Seon CHOI
  • Publication number: 20170062387
    Abstract: The semiconductor chip may include an integrated circuit on a substrate, center pad on the substrate and electrically connected to the integrated circuit, lower insulating structure on the center pad and having a contact hole exposing the center pad, redistribution layer including a conductive pattern and a barrier pattern, the barrier pattern between the lower insulating structure and the conductive pattern, the conductive patter including a contact portion filling the contact hole, bonding pad portion, and conductive line portion on the lower insulating structure and connecting the contact portion to the bonding pad portion, and an upper insulating structure on the redistribution layer and having a first opening defined therein, the first opening exposing the bonding pad portion. The upper insulating structure may include an upper insulating layer covering the lower insulating structure and the redistribution layer and a polymer layer on the upper insulating layer.
    Type: Application
    Filed: July 7, 2016
    Publication date: March 2, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seokwoo HONG, Sang-ki KIM, Kyo-Seon CHOI, Ae-Hee CHOI