Patents by Inventor Afrânio Magno da Silva, JR.

Afrânio Magno da Silva, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9299397
    Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.
    Type: Grant
    Filed: September 14, 2014
    Date of Patent: March 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Walter L. Terçariol, Richard Titov Lara Saez, Afrânio Magno da Silva, Jr.
  • Publication number: 20140376317
    Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.
    Type: Application
    Filed: September 14, 2014
    Publication date: December 25, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Walter L. Terçariol, Richard Titov Lara Saez, Afrânio Magno da Silva, JR.
  • Patent number: 8902677
    Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Walter L. Terçariol, Richard Titov Lara Saez, Afrânio Magno da Silva, Jr.
  • Publication number: 20140160862
    Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 12, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Walter L. Terçariol, Richard Titov Lara Saez, Afrânio Magno da Silva, JR.