Patents by Inventor Afshin Dadvand

Afshin Dadvand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250038055
    Abstract: Semiconductor packages are provided. In one example, a semiconductor package includes a submount. The semiconductor package further includes a semiconductor die on the submount. The submount defines a base plane, and the submount includes at least one stud protrusion extending from the base plane in a direction toward the semiconductor die.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Inventors: Afshin Dadvand, Devarajan Balaraman
  • Publication number: 20250038056
    Abstract: Semiconductor packages are provided. In one example, the semiconductor package includes a submount. The semiconductor package further includes a recess in the submount. The recess includes a bottom surface defining a recess plane. The recess further includes at least one stud protrusion extending from the recess plane. The semiconductor package further includes a semiconductor die on the at least one stud protrusion.
    Type: Application
    Filed: January 22, 2024
    Publication date: January 30, 2025
    Inventors: Afshin Dadvand, Yusheng Lin
  • Publication number: 20240421044
    Abstract: Semiconductor packages are provided. In one example, a semiconductor package includes a submount and a semiconductor die attached to the submount using a die-attach material. The semiconductor die includes a sidewall having at least one fillet reduction feature. The at least one fillet reduction feature is configured to limit a fillet height of the die-attach material along the sidewall of the semiconductor die.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Daniel Ginn Richter, Afshin Dadvand
  • Publication number: 20240355738
    Abstract: Semiconductor devices and methods are provided. In one example, a semiconductor device includes an active region comprising one or more active semiconductor cells. The semiconductor device includes a metallization structure on the active region. The metallization structure includes beryllium.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 24, 2024
    Inventors: Afshin Dadvand, Devarajan Balaraman
  • Publication number: 20240321663
    Abstract: A device may include device parts, a composite coating material arranged on one or more of the device parts, and a molding compound arranged on and/or around one or more of the device parts. Moreover, the device may include where the composite coating material may include a polymer matrix including and/or incorporating ceramic particles.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Inventors: Afshin DADVAND, Dev BALARAMAN
  • Publication number: 20240321659
    Abstract: A device includes device parts, a diamond-like based material coating arranged on one or more of the device parts. Additionally, the diamond-like based material coating may include at least one of a diamond-like carbon (DLC) material and/or a diamond-like nanocomposite (DLN) material.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Inventors: Afshin DADVAND, Dev BALARAMAN
  • Publication number: 20240282741
    Abstract: Die attach materials are provided. In one example, the die-attach material includes a plurality of core-shell particles. Each core-shell particle includes a core and a shell on the core. The core includes a conducting material. The shell includes a metal nitride.
    Type: Application
    Filed: February 15, 2023
    Publication date: August 22, 2024
    Inventors: Afshin Dadvand, Devarajan Balaraman
  • Publication number: 20240274514
    Abstract: Semiconductor packages are provided. In one example, a semiconductor package may include a substrate comprising a through hole extending through the substrate. The semiconductor package may include a semiconductor die on the substrate. The semiconductor die may be overlapping the through hole. The through hole in the substrate may be at least partially filled with an electroless deposited portion.
    Type: Application
    Filed: February 15, 2023
    Publication date: August 15, 2024
    Inventors: Afshin Dadvand, Devarajan Balaraman
  • Publication number: 20240258217
    Abstract: A semiconductor device package includes a conductive submount, a metal layer comprising a first material on the conductive submount, and at least one conductive buffer layer comprising a second material on the metal layer. The conductive buffer layer may be between the metal layer and the conductive submount, or may be between the metal layer and a transistor die on the conductive submount. The second material of the conductive buffer layer has limited or no solid solubility with respect to the first material of the metal layer. Related packages and fabrication techniques are also discussed.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 1, 2024
    Inventors: Afshin Dadvand, Devarajan Balaraman
  • Publication number: 20240182757
    Abstract: Die-attach materials are provided. In one example, the die-attach material may include a plurality of core-shell particles. Each core-shell particle may include a core and a shell on the core. The core may include a conducting material. The shell may include an alloy. The alloy may include a first element and a second element. The second element may segregate into one or more grain boundaries in the die-attach material during bonding of the die-attach material.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Inventors: Afshin Dadvand, Devarajan Balaraman
  • Patent number: 11545633
    Abstract: The development of air-stable unipolar n-type semiconductors with good solubility in organic solvents at room temperature remains a critical issue in the field of organic electronics. Moreover, most of the existing semiconducting materials exhibit LUMO energy levels higher than ?4.0 eV, making electron transport sensitive to both moisture and oxygen. Bis(2-oxoindolin-3-ylidene)benzodifurandione dicyanide or derivatives thereof are disclosed herein. More specifically, bis(2-oxoindolin-3-ylidene)benzodifurandione dicyanide or derivatives thereof for use in organic electronics are disclosed. A process for the preparation of bis(2-oxoindolin-3-ylidene)benzodifurandione dicyanide and derivatives is also disclosed. The bis(2-oxoindolin-3-ylidene)benzodifurandione dicyanide or derivatives thereof are characterized by high electron mobilities and are suitable for use as n-type semiconductors in organic electronics.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 3, 2023
    Assignees: NATIONAL RESEARCH COUNCIL OF CANADA
    Inventors: Jianping Lu, Afshin Dadvand, Mark Bortolus, Salima Alem, Ye Tao, Yuning Li, Jesse Quinn
  • Publication number: 20210013424
    Abstract: The development of air-stable unipolar n-type semiconductors with good solubility in organic solvents at room temperature remains a critical issue in the field of organic electronics. Moreover, most of the existing semiconducting materials exhibit LUMO energy levels higher than ?4.0 eV, making electron transport sensitive to both moisture and oxygen. Bis(2-oxoindolin-3-ylidene)benzodifurandione dicyanide or derivatives thereof are disclosed herein. More specifically, bis(2-oxoindolin-3-ylidene)benzodifurandione dicyanide or derivatives thereof for use in organic electronics are disclosed. A process for the preparation of bis(2-oxoindolin-3-ylidene)benzodifurandione dicyanide and derivatives is also disclosed. The bis(2-oxoindolin-3-ylidene)benzodifurandione dicyanide or derivatives thereof are characterized by high electron mobilities and are suitable for use as n-type semiconductors in organic electronics.
    Type: Application
    Filed: March 13, 2019
    Publication date: January 14, 2021
    Applicant: NATIONAL RESEARCH COUNCIL OF CANADA
    Inventors: Jianping LU, Afshin DADVAND, Mark BORTOLUS, Salima ALEM, Ye TAO, Yuning LI, Jesse QUINN
  • Patent number: 10125285
    Abstract: Disclosed is a method of printing ultranarrow-gap lines of a functional material, such as an electrically conductive silver ink. The method entails providing a substrate having an interlayer coated on the substrate and printing the ultranarrow-gap lines by depositing ink on the interlayer of the substrate, the ink comprising the functional material and a solvent that swells the interlayer to cause the interlayer to bulge at edges of the ink to thereby define embankments that confine the ink.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 13, 2018
    Assignee: National Research Council of Canada
    Inventors: Ta-Ya Chu, Christophe Py, Ye Tao, Zhiyi Zhang, Afshin Dadvand
  • Publication number: 20180187036
    Abstract: Disclosed is a method of printing ultranarrow-gap lines of a functional material, such as an electrically conductive silver ink. The method entails providing a substrate having an interlayer coated on the substrate and printing the ultranarrow-gap lines by depositing ink on the interlayer of the substrate, the ink comprising the functional material and a solvent that swells the interlayer to cause the interlayer to bulge at edges of the ink to thereby define embankments that confine the ink.
    Type: Application
    Filed: June 30, 2016
    Publication date: July 5, 2018
    Inventors: Ta-Ya Chu, Christophe Py, Ye Tao, Zhiyi Zhang, Afshin Dadvand