Patents by Inventor Agajan Suvkhanov

Agajan Suvkhanov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7429749
    Abstract: An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: September 30, 2008
    Assignee: LSI Corporation
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • Patent number: 7414721
    Abstract: An in-line, in-process or in-situ and non-destructive metrology system, apparatus and method provides composition, quality and/or thickness measurement of a thin film or multi-layer thin film formed on a substrate in a thin film processing system. Particularly, the subject invention provides a spectroscopic ellipsometer performing spectroscopic ellipsometry while the wafer is in a thin film processing system. In one form, the spectroscopic ellipsometer is associated with a wet bench system portion of the thin film processing system. The spectroscopic ellipsometer obtains characteristic data regarding the formed thin film to calculate penetration depth (Dp) for a thin film formed on the substrate. Particularly, the ellipsometer obtains an extinction coefficient (k) which is used to calculate penetration depth (Dp). Penetration depth (Dp), being a unique function of the extinction coefficient (k) provides the information for the composition, quality and/or thickness monitoring of the thin film.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: August 19, 2008
    Assignee: LSI Corporation
    Inventors: Agajan Suvkhanov, Ynhi Thi Le
  • Publication number: 20080085589
    Abstract: A strained-silicon film is disclosed. A silicon-germanium film is made by ion implantation of germanium into an epitaxial silicon layer, preferably at a temperature in the range of 200 C to 400 C. The wafer is annealed in situ or optionally after implantation. A silicon film is applied to the silicon-germanium film in a conventional manner to create the strained-silicon substrate.
    Type: Application
    Filed: November 16, 2007
    Publication date: April 10, 2008
    Applicant: LSI Logic Corporation
    Inventor: AGAJAN SUVKHANOV
  • Patent number: 7148131
    Abstract: A method for implanting ions in a semiconductor is disclosed. The method includes implanting indium ions into a substrate of a semiconductor material of the semiconductor device for a first time period. The method also includes implanting boron ions into the substrate for a second time period, wherein the first time period is initiated prior to the second time period.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: December 12, 2006
    Assignee: LSI Logic Corporation
    Inventors: Agajan Suvkhanov, Mohammad Mirabedini
  • Patent number: 7129516
    Abstract: An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: October 31, 2006
    Assignee: LSI Logic Corporation
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • Publication number: 20060163581
    Abstract: A strained-silicon film is disclosed. A silicon-germanium film is made by ion implantation of germanium into an epitaxial silicon layer, preferably at a temperature in the range of 200 C to 400 C. The wafer is annealed in situ or optionally after implantation. A silicon film is applied to the silicon-germanium film in a conventional manner to create the strained-silicon substrate.
    Type: Application
    Filed: January 24, 2005
    Publication date: July 27, 2006
    Inventor: Agajan Suvkhanov
  • Patent number: 6998343
    Abstract: A method for forming damascene interconnect copper diffusion barrier layers includes implanting calcium into the sidewalls of the trenches and vias. The calcium implantation into dielectric layers, such as oxides, is used to prevent Cu diffusion into oxide, such as during an annealing process step. The improved barrier layers of the present invention help prevent delamination of the Cu from the dielectric.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: February 14, 2006
    Assignee: LSI Logic Corporation
    Inventors: Grace Sun, Vladimir Zubkov, William K. Barth, Sethuraman Lakshminarayanan, Sey-Shing Sun, Agajan Suvkhanov, Hao Cui
  • Patent number: 6982229
    Abstract: An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: January 3, 2006
    Assignee: LSI Logic Corporation
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • Publication number: 20050167654
    Abstract: An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
    Type: Application
    Filed: April 4, 2005
    Publication date: August 4, 2005
    Inventors: Agajan Suvkhanov, Mohammad Mirabedini
  • Publication number: 20040247894
    Abstract: An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.
    Type: Application
    Filed: June 4, 2003
    Publication date: December 9, 2004
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • Publication number: 20040206950
    Abstract: An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
    Type: Application
    Filed: April 18, 2003
    Publication date: October 21, 2004
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • Publication number: 20040206951
    Abstract: An integrated circuit (IC) includes a CMOS device with a channel region that has ions implanted therein. The IC preferably incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. The ion-implanted channel region preferably has a carrier mobility that is greater than that for a region that is not implanted with the ions.
    Type: Application
    Filed: April 18, 2003
    Publication date: October 21, 2004
    Inventors: Mohammad R. Mirabedini, Agajan Suvkhanov