Patents by Inventor Agatino Massimo Maccarrone
Agatino Massimo Maccarrone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096412Abstract: In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.Type: ApplicationFiled: September 8, 2023Publication date: March 21, 2024Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (ALPS) SASInventors: Antonino CONTE, Agatino Massimo MACCARRONE, Francesco TOMAIUOLO, Thomas JOUANNEAU, Vincenzo RUSSO
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Patent number: 11848071Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: GrantFiled: December 8, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Patent number: 11803202Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.Type: GrantFiled: September 21, 2022Date of Patent: October 31, 2023Assignee: STMICROELECTRONICS S.R.L.Inventors: Marco Ruta, Antonio Conte, Michelangelo Pisasale, Agatino Massimo Maccarrone, Francesco Tomaiuolo
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Publication number: 20230283271Abstract: A system a ring oscillator configured to produce a set of clock signals having the same clock period and a mutual time delay between respective clock signal edges. Comparator circuits are coupled to first and second input nodes and produce a set of comparison signals according to a respective sequence of comparison phases. A set of synchronization circuits is coupled to the ring oscillator and to the plurality of comparator circuits. The synchronization circuits allot, to each one of the comparator circuits, respective time windows for communication over respective communication lines of the comparison signals. The respective time windows are synchronized based on the clock signals. A multiplexer couples the respective communication lines to an output line to sequentially enable each of the comparator circuits to sequentially output respective comparison signals over the output line for the respective time windows thereby forming a composite comparison signal evolving over time.Type: ApplicationFiled: January 23, 2023Publication date: September 7, 2023Inventors: Antonino Conte, Marco Ruta, Michelangelo Pisasale, Agatino Massimo Maccarrone, Francesco Tomaiuolo
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Publication number: 20230170914Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.Type: ApplicationFiled: November 10, 2022Publication date: June 1, 2023Inventors: Agatino Massimo Maccarrone, Antonino Conte, Francesco Tomaiuolo, Michelangelo Pisasale, Marco Ruta
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Publication number: 20230130268Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.Type: ApplicationFiled: September 21, 2022Publication date: April 27, 2023Inventors: Marco Ruta, Antonino Conte, Michelangelo Pisasale, Agatino Massimo Maccarrone, Francesco Tomaiuolo
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Patent number: 11621684Abstract: Memories for receiving or transmitting voltage signals might include an input or output buffer including a first stage having first and second inputs and configured to generate a current sink and source at its first and second outputs responsive to a voltage difference between its first and second inputs, and a second stage having a first input connected to the first output of the first stage, a second input connected to the second output of the first stage, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.Type: GrantFiled: October 22, 2020Date of Patent: April 4, 2023Assignee: Micron Technology, Inc.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli
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Publication number: 20230021601Abstract: In an embodiment a circuit includes a plurality of memory cells, wherein each memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal, a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses and at least one current generator circuit configured to inject a compensation current into the common control node in response to the current-modulating transistors injecting the programming currents inType: ApplicationFiled: July 22, 2022Publication date: January 26, 2023Inventors: Agatino Massimo Maccarrone, Antonino Conte, Francesco Tomaiuolo, Michelangelo Pisasale, Marco Ruta
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Publication number: 20220101898Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: ApplicationFiled: December 8, 2021Publication date: March 31, 2022Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Patent number: 11282550Abstract: Examples described herein can be used to calibrate resistances provided by pull-up and pull-down circuits in an output driver circuit. A first reference voltage can be determined and applied to set a resistance level of a pull-up circuit to a desired level. A code for activating one or more transistor in the pull-up circuit can be determined against the first reference voltage. For a pull-down circuit, a second reference voltage can be set a resistance level of the pull-down circuit to a desired level. The resistance level of the pull-down circuit can be set to equal to the resistance level of the pull-up circuit. A second code can be set for activating one or more transistor in the pull-down circuit. The first and second reference voltages can be represented by index values. The code and second code can be stored for use by the pull-up circuit and pull-down circuit. Re-calibration of the pull-up and pull-down circuits can be performed to determine codes using the first and second reference voltages.Type: GrantFiled: October 12, 2018Date of Patent: March 22, 2022Assignee: Intel CorporationInventors: Luigi Pilolli, Agatino Massimo Maccarrone, Jiawei Chen, Qiang Tang
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Patent number: 11211104Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: GrantFiled: November 6, 2020Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Patent number: 11201611Abstract: An input/output (I/O) circuit provides a direct current (DC) bias between I/O stages to control duty cycle of the I/O. The I/O circuit can include one or more predriver stages and one or more output stages. The predriver stages can collectively be referred to as a predriver stage, and the output stages can collectively be referred to an output stage. The output stage for a transmitter drives the signal line. The output stage for an input buffer provides a receive signal for processing by the receiver. The I/O circuit includes a control circuit to control the DC bias between the stages to provide trim adjustment of a duty cycle for the output stage.Type: GrantFiled: December 12, 2018Date of Patent: December 14, 2021Assignee: Intel CorporationInventors: Guan Wang, Qiang Tang, Agatino Massimo Maccarrone
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Publication number: 20210134334Abstract: Examples described herein can be used to calibrate resistances provided by pull-up and pull-down circuits in an output driver circuit. A first reference voltage can be determined and applied to set a resistance level of a pull-up circuit to a desired level. A code for activating one or more transistor in the pull-up circuit can be determined against the first reference voltage. For a pull-down circuit, a second reference voltage can be set a resistance level of the pull-down circuit to a desired level. The resistance level of the pull-down circuit can be set to equal to the resistance level of the pull-up circuit. A second code can be set for activating one or more transistor in the pull-down circuit. The first and second reference voltages can be represented by index values. The code and second code can be stored for use by the pull-up circuit and pull-down circuit. Re-calibration of the pull-up and pull-down circuits can be performed to determine codes using the first and second reference voltages.Type: ApplicationFiled: October 12, 2018Publication date: May 6, 2021Inventors: Luigi PILOLLI, Agatino Massimo MACCARRONE, Jiawei CHEN, Qiang TANG
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Publication number: 20210057007Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: ApplicationFiled: November 6, 2020Publication date: February 25, 2021Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Publication number: 20210044266Abstract: Memories for receiving or transmitting voltage signals might include an input or output buffer including a first stage having first and second inputs and configured to generate a current sink and source at its first and second outputs responsive to a voltage difference between its first and second inputs, and a second stage having a first input connected to the first output of the first stage, a second input connected to the second output of the first stage, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.Type: ApplicationFiled: October 22, 2020Publication date: February 11, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli
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Publication number: 20200402554Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: ApplicationFiled: June 20, 2019Publication date: December 24, 2020Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Patent number: 10861517Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: GrantFiled: June 20, 2019Date of Patent: December 8, 2020Assignee: Micron Technology, Inc.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Patent number: 10819296Abstract: Apparatus useful for receiving or transmitting voltage signals might include a current generator having first and second inputs and configured to generate a current flow between first and second outputs responsive to a voltage difference between its first and second inputs. The apparatus might further include a feedback amplifier having a first input connected to the first output of the current generator, a second input connected to the second output of the current generator, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.Type: GrantFiled: March 22, 2019Date of Patent: October 27, 2020Assignee: Micron Technology, Inc.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli
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Publication number: 20200304086Abstract: Apparatus useful for receiving or transmitting voltage signals might include a current generator having first and second inputs and configured to generate a current flow between first and second outputs responsive to a voltage difference between its first and second inputs. The apparatus might further include a feedback amplifier having a first input connected to the first output of the current generator, a second input connected to the second output of the current generator, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.Type: ApplicationFiled: March 22, 2019Publication date: September 24, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli
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Publication number: 20200195239Abstract: An input/output (I/O) circuit provides a direct current (DC) bias between I/O stages to control duty cycle of the I/O. The I/O circuit can include one or more predriver stages and one or more output stages. The predriver stages can collectively be referred to as a predriver stage, and the output stages can collectively be referred to an output stage. The output stage for a transmitter drives the signal line. The output stage for an input buffer provides a receive signal for processing by the receiver. The I/O circuit includes a control circuit to control the DC bias between the stages to provide trim adjustment of a duty cycle for the output stage.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Guan WANG, Qiang TANG, Agatino Massimo MACCARRONE