Patents by Inventor Agere Systems LLC

Agere Systems LLC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130203396
    Abstract: A method of using an intercom on a cordless telephone during an active call. The active call is put on hold while the intercom is in use. Once the call is re-activated, the intercom is shut off. This system may be designed for a cordless telephone with one handset or a plurality of handsets.
    Type: Application
    Filed: March 11, 2013
    Publication date: August 8, 2013
    Applicant: Agere Systems LLC
    Inventor: Agere Systems LLC
  • Publication number: 20130156086
    Abstract: Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame marker and a predefined binary value in an output of the logic function.
    Type: Application
    Filed: February 14, 2013
    Publication date: June 20, 2013
    Applicant: Agere Systems LLC
    Inventor: Agere Systems LLC
  • Publication number: 20130120867
    Abstract: Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft-output detector is provided for processing a received signal, comprising: a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states. A method is provided for processing a received signal using a soft-output detector, comprising: calculating forward state metrics using a forward detector; calculating backward state metrics using a backward detector; and calculating a current branch metric using a current branch detector, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states.
    Type: Application
    Filed: January 8, 2013
    Publication date: May 16, 2013
    Applicant: Agere Systems LLC
    Inventor: Agere Systems LLC
  • Publication number: 20130104096
    Abstract: One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 25, 2013
    Applicant: AGERE SYSTEMS LLC
    Inventor: AGERE SYSTEMS LLC
  • Publication number: 20130094345
    Abstract: In one embodiment, an algorithm dynamically selects a method for reducing distortion in a multi-carrier modulated signal, such as an orthogonal frequency division multiplexing (OFDM) signal. The algorithm directs a transmitter to transmit peak-to-average power ratio (PAPR)-reduction signals over reserved tones (i.e., frequencies) if reserved tones are available. If reserved tones are not available, then the algorithm directs the transmitter to transmit PAPR-reduction symbols over free tones if free tones are available. If the free tones for this transmitter are used by adjacent transmitters, then interference-reduction techniques may be used to reduce interference with the adjacent transmitters. If reserved tones and free tones are not available, then the transmitter may use an alternative method to reduce distortion, such as successive clipping and filtering. In another embodiment, the transmitter may transmit PAPR-reduction symbols over both free and reserved tones, if available.
    Type: Application
    Filed: December 4, 2012
    Publication date: April 18, 2013
    Applicant: Agere Systems LLC
    Inventor: Agere Systems LLC
  • Publication number: 20130088256
    Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.
    Type: Application
    Filed: November 30, 2012
    Publication date: April 11, 2013
    Applicant: AGERE SYSTEMS LLC
    Inventor: AGERE SYSTEMS LLC
  • Publication number: 20130056868
    Abstract: The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.
    Type: Application
    Filed: October 19, 2012
    Publication date: March 7, 2013
    Applicant: AGERE SYSTEMS LLC
    Inventor: Agere Systems LLC
  • Publication number: 20130058464
    Abstract: In one embodiment, the presence of double talk (DT) is detected in a telecommunications network having a near-end user and a far-end user. The energies of both (1) a signal received from the far-end user by the near-end user and (2) a signal to be communicated from the near-end user to the far-end user are computed. An echo return loss (ERL) estimate is calculated based on the energy calculations, and a preliminary decision is made as to whether DT is present based on the ERL estimate and the energy calculations. If DT is detected, then a counter is set to a hangover value. If DT is not detected, then the counter is reduced. This process is repeated, and, for each iteration, a final decision as to whether DT is present is made based on the counter value.
    Type: Application
    Filed: November 2, 2012
    Publication date: March 7, 2013
    Applicant: Agere Systems LLC
    Inventor: Agere Systems LLC