Patents by Inventor Agerico L. Esquirel

Agerico L. Esquirel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5909628
    Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: June 1, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Theodore W. Houston, Ih-Chin Chen, Agerico L. Esquirel, Somnath Nag, Iqbal Ali, Keith A. Joyner, Yin Hu, Jeffrey Alan McKee, Peter Stewart McAnally