Patents by Inventor Agerico L. Esquivel
Agerico L. Esquivel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6201277Abstract: A programmable memory device having slot trenches (14). A plurality of floating gates (22) are separated from a surface of semiconductor body (10) by a gate dielectric (24). A plurality of slot trenches (14) isolate memory cells (12) from each other. Each of the slot trenches (14) extends below the surface of the semiconductor body (10) between adjacent floating gates (22). A control gate (20) extends over the floating gates (22) and a portion of each of the slot trenches (14).Type: GrantFiled: June 7, 1995Date of Patent: March 13, 2001Assignee: Texas Instruments IncorporatedInventor: Agerico L. Esquivel
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Patent number: 5306935Abstract: A nonvolatile memory array has two or more stacked layers of memory cells (10). The bottom layer may comprise a planar, X-cell, or buried N++ FAMOS transistor array and the top layer preferably comprises a planar transistor array. An epitaxial silicon layer (36) provides the substrate for the second layer. The stacked layer structure allows a two-fold increase in memory density without scaling the device sizes.Type: GrantFiled: June 17, 1992Date of Patent: April 26, 1994Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Allan T. Mitchell
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Patent number: 5084418Abstract: Bitlines (34) are formed by creating a diffused region (26) around the sidewalls and bottom of a trench (20). The trench (20) is filled with a conductive region (30), typically a refractory metal, refractory metal silicide.Type: GrantFiled: January 16, 1990Date of Patent: January 28, 1992Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Howard L. Tigelaar, Allan T. Mitchell
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Patent number: 5053839Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.Type: GrantFiled: August 21, 1990Date of Patent: October 1, 1991Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Allan T. Mitchell, Howard L. Tigelaar
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Patent number: 5045490Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit lines resistivity for a given cell density.Type: GrantFiled: August 21, 1990Date of Patent: September 3, 1991Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Allan T. Mitchell, Howard L. Tigelaar
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Patent number: 5028553Abstract: A non-volatile cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines from the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.Type: GrantFiled: June 5, 1990Date of Patent: July 2, 1991Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Allan T. Mitchell
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Patent number: 5008722Abstract: A cross point EPROM array has trenches to provide improved isolation between adjacent buried N+ bitlines at locations where the adjacent buried N+ bitlines are not separated by a FAMOS transistor. This results in improved leakage current, improved punchthrough voltage characteristics, and in improved programmability for the cell.Type: GrantFiled: May 31, 1989Date of Patent: April 16, 1991Assignee: Texas Instruments IncorporatedInventor: Agerico L. Esquivel
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Patent number: 4979004Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.Type: GrantFiled: January 23, 1990Date of Patent: December 18, 1990Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Allan T. Mitchell, Howard L. Tigelaar
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Patent number: 4977439Abstract: A method and apparatus for providing interconnections between levels on a semiconductor substrate of various types includes first forming a plurality of trenches in the substrate and then forming conductive layers at the bottom of the trenches. The trenches are then filled with an oxide to provide a planar surface on the substrate. Various levels of trenches are provided with crossovers being formed by a bridging layer of a conductive material that is formed over an oxide layer in the lower level trenches. Vertical contacts are formed by etching an opening from the surface to the bottom of the trenches through the oxide layer and filling the opening with a metal plug.Type: GrantFiled: April 3, 1987Date of Patent: December 11, 1990Inventors: Agerico L. Esquivel, Allan T. Mitchell
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Patent number: 4951103Abstract: A non-volatie cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines form the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.Type: GrantFiled: June 3, 1988Date of Patent: August 21, 1990Assignee: Texas Instruments, IncorporatedInventors: Agerico L. Esquivel, Allan T. Mitchell
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Patent number: 4905062Abstract: A sealed gate FAMOS transistor (28) disposes a thermal oxide layer (40) about the floating gate (34) in order to isolate the floating gate (34) from the planar isolating regions (44) between floating gates (34). Trench isolating regions (54) are provided between control gates (50) to enhance programmability of the sealed gate FAMOS transistor (28).Type: GrantFiled: February 17, 1989Date of Patent: February 27, 1990Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Allan T. Mitchell
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Patent number: 4892840Abstract: Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.Type: GrantFiled: April 11, 1989Date of Patent: January 9, 1990Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Robert Groover, III, Howard L. Tigelaar
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Patent number: 4855800Abstract: Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.Type: GrantFiled: September 11, 1987Date of Patent: August 8, 1989Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Robert Groover, III, Howard L. Tigelaar
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Patent number: 4833514Abstract: The invention provides an EPROM having a high quality dielectric to separate the floating gate from low quality dielectric layers used in the prior art by the method outlined as follows. First, the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1:1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface.Type: GrantFiled: November 18, 1987Date of Patent: May 23, 1989Assignee: Texas Instruments IncorporatedInventors: Agerico L. Esquivel, Allan T. Mitchell
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Patent number: 4698900Abstract: A cross point EPROM array has trenches to provide improved isolation between adjacent buried N+ bitlines at locations where the adjacent buried N+ bitlines are not separated by a FAMOS transistor. This results in improved leakage current, improved punchthrough voltage characteristics, and in improved programmability for the cell.Type: GrantFiled: March 27, 1986Date of Patent: October 13, 1987Assignee: Texas Instruments IncorporatedInventor: Agerico L. Esquivel